DS33X41+ Maxim Integrated Products, DS33X41+ Datasheet - Page 57
![IC MAPPING ETHERNET 256CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS33X41+
Manufacturer Part Number
DS33X41+
Description
IC MAPPING ETHERNET 256CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33X11.pdf
(375 pages)
Specifications of DS33X41+
Applications
Data Transport
Interface
Parallel/Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
256-CSBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.12.4 Alarms and Conditions related to VCAT/LCAS
The latched status bits for the VCAT/LCAS sequence (VCAT.RSLSR.SQL), control (VCAT.RSLSR.CTRL) and
RS-Ack (VCAT.RSLSR.RSACKL) bits can be used to generate device interrupts on a change of state.
The latched Loss of Multiframe Sync (VCAT.RSLSR.LOML), Realign (VCAT.RRLSR.REALIGN[1-4]) and
Differential Delay (VCAT.RRLSR.DDE[1-4]) bits can be used to generate an interrupt upon transition from the
inactive (normal) to the active (alarm) state. If the user’s application requires an indication of the transition from the
active to inactive condition, the host processor should poll the (non-latched) status bits to determine when the
alarm becomes inactive.
8.13 Arbiter/Buffer Manager
The Arbiter manages the transport between the Ethernet and Serial ports. It is responsible for queuing and
dequeuing frames to a single external SDRAM. The arbiter handles requests from the Packet Processor and MAC
to transfer data to and from the SDRAM. For more information of how the Arbiter settings affect QoS, see Section
8.16. For more information on configuring the Arbiter’s interactions with the SDRAM queues, see Section 8.9.3.
Rev: 063008
57 of 375
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