DS33X41+ Maxim Integrated Products, DS33X41+ Datasheet
![IC MAPPING ETHERNET 256CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS33X41+
Specifications of DS33X41+
Related parts for DS33X41+
DS33X41+ Summary of contents
Page 1
... Supplies ♦ IEEE 1149.1 JTAG Support Features continued in Section 2. PART Applications DS33X162+ DS33X161+ DS33X82+ DS33X81+ DS33X42+ DS33X41+ DS33X11+ DS33W41+ DS33W11+ Note: All devices are specified over the -40 QoS operating temperature range. POLICY ENET +Denotes a lead-free/RoHS-compliant package. PHYs BRIDGING SPI is a trademark of Motorola, Inc ...
Page 2
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 1. DETAILED DESCRIPTION .............................................................................................................. 9 2. FEATURE HIGHLIGHTS................................................................................................................ 10 2.1 G ...................................................................................................................................... 10 ENERAL 2.2 VCAT/LCAS L A INK GGREGATION 2.3 HDLC........................................................................................................................................... 10 2.3.1 cHDLC.................................................................................................................................................. 10 2.4 GFP-F.......................................................................................................................................... 11 2.5 X.86 S .............................................................................................................................11 UPPORT 2.6 DDR SDRAM I ...
Page 3
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8 ESETS AND OW OWER 8 NITIALIZATION AND ONFIGURATION 8 ....................................................................................................................41 LOBAL ESOURCES 8 ORT ESOURCES 8 .....................................................................................................................41 EVICE NTERRUPTS 8 ORWARDING ODES ...
Page 4
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 9 NTERFACING TO AXIM 9 NTERFACING TO AXIM 10. DEVICE REGISTERS................................................................................................................... 105 10 EGISTER IT APS 10.1.1 Global Register Bit Map ..................................................................................................................... 106 10.1.2 MAC Indirect Register Bit Map........................................................................................................... 131 10.2 ...
Page 5
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 13.2.2 BYPASS............................................................................................................................................. 367 13.2.3 EXTEST ............................................................................................................................................. 367 13.2.4 CLAMP............................................................................................................................................... 367 13.2.5 HIGHZ ................................................................................................................................................ 367 13.2.6 IDCODE ............................................................................................................................................. 367 13.3 JTAG ID C ......................................................................................................................368 ODES 13 .....................................................................................................................368 EST EGISTERS 13.4.1 Boundary Scan Register .................................................................................................................... 368 13.4.2 Bypass ...
Page 6
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 3-1. Standardized Ethernet Transport over Multiple T1/E1 Lines .................................................................. 14 Figure 3-2. Standardized Ethernet Transport over a Single T1/E1 Line ................................................................... 15 Figure 3-3. Remote IP DSLAM T1/E1 Trunk Card .................................................................................................... 16 Figure 6-1. Simplified Logical Block ...
Page 7
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 11-19. GMII Receive Interface Functional Timing ........................................................................................ 336 Figure 11-20. MII Transmit Functional Timing......................................................................................................... 337 Figure 11-21. MII Transmit Half Duplex with a Collision Functional Timing ............................................................ 337 Figure 11-22. MII Receive Functional Timing.......................................................................................................... 337 Figure 11-23. ...
Page 8
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 1-1. Product Selection Matrix............................................................................................................................. 9 Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 21 Table 8-1. Clocking Options for the Ethernet Interface ............................................................................................. 37 Table 8-2. Software Reset Functions ........................................................................................................................ 39 Table 8-3. Block Enable Functions ............................................................................................................................ 40 Table ...
Page 9
... The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply. The DDR interface also requires a 1.25V reference voltage that can be obtained through a resistor-divider network. Table 1-1. Product Selection Matrix Ordering Ethernet TDM Number Ports Ports 1 1 DS33X11+ 10/100/GbE 1 DS33W11+ 1 10/100/GbE 1 DS33X41+ 4 10/100/GbE 1 DS33W41+ 4 10/100/GbE 2 10/100 DS33X42 GbE 1 DS33X81+ 8 10/100/GbE 2 10/100 DS33X82+ 8 ...
Page 10
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 2. Feature Highlights 2.1 General • 17mm 256 pin CSBGA Package (DS33X162/X161/X82/X81/X41/W41/W11) • 10mm 144 pin CSBGA Package (DS33X11) • 1.8V, 2.5V, 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon ...
Page 11
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 2.4 GFP-F • GFP Frame mode per ITU-T G.7041 • GFP idle frame insertion and extraction • Supports Null and Linear headers • cHEC based frame delineation 43 • payload and Barker Sequence scrambling/descrambling • CSF ...
Page 12
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 2.7.1 Ethernet Bridging for 10/100 • 4K Address and VLAN ID lookup table for Learning and Filtering • Programmable Aging between 1 to 300 seconds in 1 second intervals 2.7.2 Ethernet Traffic Classification • Ingress Classification according to ...
Page 13
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 2.8 Serial Ports • Four, Eight or Sixteen Serial ports with Synchronous Clock/Data at 128kbps to 52MHz. • Independently clock inputs for RX and TX operations on the per port bases. • Input clock supports either continuous or ...
Page 14
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 3. Applicable Equipment Types ♦ Bonded Transparent LAN Service ♦ LAN Extension ♦ Ethernet Delivery over T1/E1/J1, T3/E3, xDSL, V.35/Optical Figure 3-1. Standardized Ethernet Transport over Multiple T1/E1 Lines 10/100/ 10/100/1000 1000 ETHERNET PHY 10/100 10/100/ ETHERNET PHY ...
Page 15
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 3-2. Standardized Ethernet Transport over a Single T1/E1 Line 10/100/1000 ETHERNET 10/100/ 1000 PHY DDR SDRAM RS-232 CONFIG SOLUTION ADVANTAGES: • Ethernet Transport Over Single or Fractional E1/T1 with QoS and Ethernet OAM Capability! • Flexible Fractional ...
Page 16
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 3-3. Remote IP DSLAM T1/E1 Trunk Card xDSL LINE CARD xDSL LINE CARD xDSL LINE CARD TO SUBSCRIBERS xDSL LINE CARD SOLUTION ADVANTAGES: • Standards Compliant Ethernet Transport Over Multiple E1/T1 Links • QoS and Ethernet OAM ...
Page 17
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 4. Acronyms & Glossary • CLE - Customer Located Equipment. • CoS - Class of Service, 802.1Q defined three User priority bits in Tag control Info Field. • DCE - Data Communication Interface. • DSCP - Diff Serve ...
Page 18
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 5. Designing with the DS33X162 Family of Devices The DS33X162 family of products provide the required flexibility and complexity to meet the needs of a very broad range of applications. Although typical applications using these devices are very ...
Page 19
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 5.3 Ancillary Device Selection All devices in the product family require an external DDR SDRAM for operation. The user must select a JEDEC JESD79D compliant DDR SDRAM. DDR 266 or faster may be used. The recommended size is ...
Page 20
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 6. Block Diagrams Figure 6-1. Simplified Logical Block Diagram TCLK1 TRANSMIT SERIAL TDATA1 PORT 1 TSYNC1 TCLK2 TRANSMIT SERIAL TDATA2 PORT 2 TSYNC2 TMCLK4 TRANSMIT SERIAL TDATA16 PORT 16 TMSYNC4 RCLK1 RECEIVE SERIAL RDATA1 PORT 1 RSYNC1 RCLK2 ...
Page 21
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 7. Pin Descriptions 7.1 Pin Functional Description Note that all digital pins are inout pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. Table 7-1. Detailed Pin Descriptions PACKAGE PINS NAME 256 144 ...
Page 22
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 D5 SPI_SWAP D6 SPI_CPHA D7 SPI_CPOL RD/DS J9 — WR/RW J10 — ALE J7 — MODE J12 — INT J11 G5 SPI_SEL J16 — ...
Page 23
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 TXD[0]/TXD1[0], J13, J8, TXD[1]/TXD1[1], K15, J9, TXD[2]/TXD1[2], J15, H8, TXD[3]/TXD1[3], H13, H9, TXD[4]/TXD2[0], N15, L8, TXD[5]/TXD2[1], P15, K8, TXD[6]/TXD2[2], R15, L9, TXD[7]/TXD2[3] T15 K9 RXD[0]/RXD1[0], G14, J10, RXD[1]/RXD1[1], F13, J11, RXD[2]/RXD1[2], F14, H10, ...
Page 24
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 TX_EN1, K14, F8 TX_EN2 P16 RX_DV1, G15, F9 RX_DV2 M11 RX_CRS1, E13, G12 RX_CRS2 J14 RX_ERR1, H15, G9 RX_ERR2 M12 TX_ERR1, L14, G8 TX_ERR2 R16 COL1, E14, G10 COL2 L16 DCEDTES P13 L7 ...
Page 25
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 REF_CLK T13 M8 GTX_CLK R14 M10 MDC F15 H5 MDIO G13 H4 SDATA[0] C16 A11 SDATA[1] B16 B11 SDATA[2] B15 D11 SDATA[3] C15 C11 SDATA[4] A14 A10 SDATA[5] C12 B10 SDATA[6] A13 D10 ...
Page 26
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 SRAS A6 B5 SCAS B7 D5 SWE A7 C5 SD_UDM D7 E7 SD_LDM D13 E6 SD_LDQS C13 E8 SD_UDQS D8 D7 SD_CLK A8 A8 SD_CLK A9 A7 SD_CLKEN C4 E5 TDATA1 T6 L3 ...
Page 27
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 TCLK5/TMCLK2 M7 — TCLK6 P10 — TCLK7 T10 — TCLK8 R10 — TMCLK3 T11 — TMCLK4 M10 — TSYNC1 TMSYNC1 TSYNC2 T8 — TSYNC3 M6 — TSYNC4 P7 — TSYNC5/ R7 ...
Page 28
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 RCLK1 E1 G1 RCLK2 G7 — RCLK3 G1 — RCLK4 H4 — RCLK5 F4 — RCLK6 J1 — RCLK7 J5 — RCLK8 J4 — RCLK9 J3 — RCLK10 J2 — RCLK11 M2 — ...
Page 29
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 RVSYNC F4 — RVDEN G3 — HIZ H16 F10 RST E8 F2 SYSCLKI E16 E12 JTRST B1 G4 JTCLK A1 G3 JTDO E2 H2 JTDI D2 H3 JTMS C1 G2 E10, F3, E12, ...
Page 30
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 PACKAGE PINS NAME 256 144 A10, C7, F6, F8, F9, F6, F7, F10, F12, F11, G11, F16, J6, J7, G6, K1, K2, VSS G9, K6, L6, H5, M1, H9, M6, H10, M9, M12 M13, R4, T5 AVDD F5 ...
Page 31
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 7-1. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33X162/X161/X82/X81/X42/X41 SDCS A JTCLK SDA[3] SDA[10] SDA[12] B JTRST SDA[2] SBA[1] SBA[0] SD_CLKE C JTMS SDA[1] SDA[ RDATA1 JTDI SDA[4] SDA[5] E RCLK1 JTDO ...
Page 32
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 7-2. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33W41/DS33W11 SDCS A JTCLK SDA[3] SDA[10] SDA[12] B JTRST SDA[2] SBA[1] SBA[0] SD_CLKE C JTMS SDA[1] SDA[ RDATA1 JTDI SDA[4] SDA[5] E RCLK1 JTDO ...
Page 33
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 7-3. 144-Ball, 10mm x 10mm, CSBGA Pinout (DS33X11 VSS VDDQ SDA[0] B VDD2.5 SDA[2] SDA[8] C SDA[4] SDA[6] SDA[10] D SDA[3] SDA[1] SDA[12] E SDA[5] SDA[7] VSS F VDD1.8 RST VDD3.3 G RCLK1 ...
Page 34
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8. Functional Description The DS33X162 family of devices provide interconnection and mapping functionality between Ethernet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, T3/E3, and SONET/SDH. The device is composed two 10/100/1000 ...
Page 35
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.1 Parallel Processor Interface Configuration and control can be accomplished through the 8-bit parallel microprocessor port. The device’s 16-bit registers are accessed as sequential byte addresses. The 8-bit parallel data bus can be configured for Intel or Motorola ...
Page 36
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.2 SPI Serial Processor Interface The SPI interface is a four-signal serial interface that allows configuration and monitoring of the device with a minimal number of electrical connections. The SPI interface uses Full-Duplex SPI Slave operation. The maximum ...
Page 37
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.3 Clock Structure The clock sources and functions are as follows: • Serial Transmit Data (TCLKn) and Serial Receive Data (RCLKn) clock inputs are used to transfer data from the serial interface. These clocks can be continuous or ...
Page 38
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-1. Clocking Diagram TCLK1 TRANSMIT SERIAL PORT 1 TCLK2 TRANSMIT SERIAL PORT 2 TMCLK4 TRANSMIT SERIAL PORT 16 RCLK1 RECEIVE SERIAL PORT 1 RCLK2 RECEIVE SERIAL PORT 2 RCLK16 RECEIVE SERIAL PORT 16 VOICE PORT Rev: 063008 ...
Page 39
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.3.1 Serial Interface Clock Modes Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLK and RCLK) are inputs, and can be gapped. 8.3.2 Ethernet Interface Clock Modes The Ethernet interfaces can ...
Page 40
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 There are several features included to reduce power consumption. The reset bits of the LI.RCR1.RFRST, LI.RVPCR.RVRST, LI.TVPCR.TVFRST, and VCAT.RCR4.RFRST registers also place the associated circuitry in a low-power mode. Additionally, the RST pin may be held low indefinitely ...
Page 41
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.5 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device STEP 2: Configure Serial Ports, TX VCAT, RX VCAT, Encapsulator, Decapsulator STEP 3: Enable transmit serial, transmit VCAT, Encapsulator, Receive LAN STEP 4: Enable transmit ...
Page 42
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-2. Device Interrupt Information Flow Diagram RCV LAN 1 SU.LIQOS MAC 1 SU.MMCRSR (MAC1) RCV LAN 2 SU.LIQOS MAC 2 SU.MMCRSR (MAC2) XMT LAN SU.WOS ENCAPSULATOR PP.ESMLS[1-4] DECAPSULATOR PP.DMLSR[1-4] XMT SERIAL LI.TVFLSR ARBITER AR.LQOS AR.WQOS AR.LQNFS AR.WQNFS ...
Page 43
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.9 Forwarding Modes and WAN Connections The path any given frame takes through the device can be determined by the contents of the frame, the port of entry, the user configured WAN Connections, and the user configured Forwarding ...
Page 44
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-3. Forwarding Mode 1: Single Ethernet Port with Priority Forwarding WAN Ports Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4 Serial Port 5 Serial TRANSMIT: Port 6 The 16 Serial Ports Serial are ...
Page 45
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-4. Forwarding Mode 2: One or Two Ethernet Port Forwarding with Scheduling WAN Ports Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4 Serial Port 5 Serial TRANSMIT: Port 6 The 16 Serial Ports ...
Page 46
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-5. Forwarding Mode 3: Single Ethernet Port with LAN-VLAN Forwarding WAN Ports Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4 Serial Port 5 Serial TRANSMIT: Port 6 The 16 Serial Ports Serial are ...
Page 47
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-6. Forwarding Mode 4: 1 Ethernet port with Port ID and LAN-VLAN Forwarding WAN Ports Serial Port 1 Serial Port 2 Serial Port 3 Serial Port 4 Serial Port 5 Serial TRANSMIT: Port 6 The 16 Serial ...
Page 48
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-7. Forwarding Mode 5: Full LAN-to-WAN and WAN-to-LAN VLAN Forwarding WAN Ports Note: Frames in each pair of WAN Serial groups are Port 1 scheduled by a Serial round-robin Port 2 scheduler. Serial Port 3 Serial Port ...
Page 49
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 The user may choose to disable unused features in a forwarding mode. In the forwarding modes with Priority Forwarding or Priority Scheduling, both 802.1p VLAN PCP and DSCP are supported. The user-programmable Priority Table is accessed through the ...
Page 50
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.9.3 Queue Configuration The starting and ending locations for each queue in DDR SDRAM are user-configured. The address space of a 256 Mbit DDR SDRAM is 24-bits, providing an address range covering 16M 16-bit words. To reduce the ...
Page 51
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.10 Bandwidth Capabilities (Throughput) All devices in the product family support approximately 416Mbps aggregate throughput. However, on the high-port count devices with dual Ethernet Interfaces (the DS33X162 and DS33X82 necessary to conform to certain constraints when ...
Page 52
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.11 Serial (WAN) The Serial Interfaces support time-division multiplexed, serial data I 52Mbps. The Serial Interface receives and transmits encapsulated Ethernet frames, and consists of a physical serial port with a GFP/X.86/HDLC/cHDLC engine. Each physical interface ...
Page 53
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.12 Link Aggregation and Link Capacity Adjustment (VCAT/LCAS) Virtual Concatenation (VCAT) allows information to be transmitted over aggregated WAN links. The VCAT function aligns all members of the VCG to the link with the most ...
Page 54
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.12.1 VCAT/LCAS Control Frame for T3/E3 Table 8-7. VCAT/LCAS Control Frame for T3/E3 Bit 1 Bit 2 Bit 3 Control Packet MST (1-4) MST (5- RESERVED (0000) RESERVED (0000) RESERVED (0000) RESERVED (0000 Bits ...
Page 55
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.12.2 VCAT/LCAS Configuration and Operation VCAT/LCAS setup requires an external Micro to issue an instruction to setup and tear down the IMUX function. The microprocessor can turn off links that are not participating. Once any changes to the ...
Page 56
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.12.3 Link Capacity Adjustment Scheme (LCAS) The Link Capacity Adjustment Scheme (LCAS) provides the capability to add and remove members from a VCAT VCG. If LCAS is enabled viaVCAT.RCR2.LE[3:0], the receive LCAS block will extract all LCAS frame ...
Page 57
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.12.4 Alarms and Conditions related to VCAT/LCAS The latched status bits for the VCAT/LCAS sequence (VCAT.RSLSR.SQL), control (VCAT.RSLSR.CTRL) and RS-Ack (VCAT.RSLSR.RSACKL) bits can be used to generate device interrupts on a change of state. The latched Loss of ...
Page 58
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.14 Flow Control In some applications, Flow Control may be required to ensure that data queues do not overflow and frames are not dropped. The device allows for optional IEEE 802.3 Compliant flow control. There are 2 basic ...
Page 59
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.14.1 Full Duplex Flow control Automatic flow control is governed by the LAN Queue high watermark in AR.LQW, and is enabled per LAN Queue in the SU.LQXPC register. This allows the user to enable or disable flow control ...
Page 60
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.15 Ethernet Interfaces The Ethernet Interface allows for direct connection to Ethernet PHYs. The interface consists of a dual 10/100Mbps MII/RMII interface or a single 1000Mbps GMII interface and associated Ethernet MACs. In GMII operation, the interface contains ...
Page 61
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 8-8. Configuration Recommendations for Maximum Frame Length Maximum Frame SU.MPL Length (bytes) 1518 1518 2048 2048 9018 9018 10240 10240 Table 8-9. Selection of MAC Interface Modes for Port 1 Function RMII_SEL Pin GMII 0 RMII 1 ...
Page 62
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.15.1 GMII Mode GMII interface operates synchronously from the external 125MHz reference, and 23 signals are required. The following figure shows the GMII architecture. Note that DCE mode is not supported for GMII mode and that GMII is ...
Page 63
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.15.2 MII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS low. MII interface operates synchronously from the external 25MHz reference (REF_CLK). The following figure shows the MII architecture. Figure 8-10. ...
Page 64
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 8-11. MII Mode Options Mode/Speed 10Mbps full duplex DTE Mode with no flow control 100Mbps full duplex, DTE Mode with flow control 100Mbps full duplex, DTE Mode with no flow control 100Mbps full duplex DCE Mode with ...
Page 65
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.15.3 DTE and DCE Mode When in 10/100 mode, the Ethernet MII interface(s) can be configured for DCE or DTE Mode. When configured in DTE Mode, direct connection can be made to Ethernet PHYs. In DCE mode, the ...
Page 66
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.15.4 RMII Mode The Ethernet interface can be configured for RMII operation by setting the hardware pin RMIIMIIS high. RMII interface operates synchronously from the external 50MHz reference (REF_CLK). Only 7 signals are required. The following figure shows ...
Page 67
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.16 Quality of Service (QoS) Features The device contains several features designed to provide Quality of Service (QoS). These features include Virtual LAN (VLAN) Forwarding and Priority Scheduling/Forwarding supporting both VLAN 802.1p and DSCP. The device also includes ...
Page 68
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.16.2 Programming the VLAN ID Table A 4 kilobyte user-configured “VLAN Table” is used to translate VLAN tag information from each received frame into forwarding, trapping (frame extraction), or discarding decisions. Each address in the table corresponds to ...
Page 69
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.16.3 Priority Coding with VLAN Tags (IEEE 802.1p) The IEEE 802.1Q VLAN tagging standard allocated room for a priority code that was later defined by the IEEE 802.1p standard. IEEE 802.1p eventually became part of IEEE 802.1D. With ...
Page 70
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.16.4 Priority Coding with Multiple (Q-in-Q) VLAN Tags Device operation with multiple VLAN tags is similar to operation with a single VLAN tag. The Ethernet Q-in-Q format is similar to the case outlined above, except that a second ...
Page 71
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.16.5 Priority Coding with DSCP The IETF RFC2474 (Differentiated Services) defines a Layer-3 alternate to 802.1p priority coding, known as Differentiated Services Code Point (DSCP). DSCP is composed of a 6-bit value located in the second byte of ...
Page 72
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.16.6 Programming the Priority Table The user-programmable Priority Table is accessed indirectly through the SU.PTC, SU.PTAA, SU.PTWD, SU.PTRD, and SU.PTSA registers. The device contains a single table, with the MSB of the table address (SU.PTAA.PTAA) used to distinguish ...
Page 73
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 8-13. Example Priority Table Configuration for PCP PTAA[6:1] 000000 000001 000010 000011 000100 000101 000110 000111 Rev: 063008 SU.PTWD/ SU.PTRD 375 ...
Page 74
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.17 OAM support with Frame Trapping, Extraction, and Insertion The device has the ability to insert and extract frames from/to the host microprocessor from both the WAN interface and the LAN interface. There are four user-accessible FIFOs for ...
Page 75
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-16. Supported Trapped Ethernet Frame Types Byte VLAN Tagged DIX # Destination Destination Address Address Source Source Address Address Ethernet Type 13 VLAN 14 ...
Page 76
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.17.1 Frame Trapping Frames from the LAN interface can be trapped by VLAN ID, Ethernet Type, Broadcast Address, Management Multicast Address (01:80:C2:xx:xx:xx), Destination Address range of Destination Addresses. Frames from the WAN interface can be trapped ...
Page 77
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.17.1.5WAN-VLAN Trapping When trapping frames received on the WAN interface by VLAN ID, the user configures the VLAN IDs (VIDs trapped using the WAN-VLAN Table. Trapping is then enabled or disabled with the SU.WEM.WEVIT bit. See ...
Page 78
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 3. Select the appropriate FIFO for insertion via GL.MCR1. 4. Write the size of frame in bytes to GL.MCR3 for LAN insertion, GL.MCR2 for WAN insertion. 5. Write the frame to the GL.MFAWR.WPKT[0:7], one byte at a time. ...
Page 79
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.18 Bridging and Filtering The Automatic Learning and Filtering functions for Ethernet Bridging are only applicable in 10/100Mbps Ethernet applications. The static DA filtering functions available in the MAC may be used for 1000Mbps applications as described in ...
Page 80
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.19 Ethernet MAC Indirect addressing is required to access the Ethernet MAC registers. Writing to the Ethernet MAC registers requires address and data information to be loaded into multiple registers, and the write operation initiated through a control ...
Page 81
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 8-14. MAC Control Registers INDIRECT ADDRESS 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch 0040h 0044h 0048h 004Ch 0050h 0054h 0058h 005Ch 0060h 0064h 0068h 006Ch 0070h 0074h 0078h 007Ch 0080h 0084h 0088h 008Ch 0090h 0094h 0098h ...
Page 82
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 8-16. MAC Counter Registers INDIRECT ADDRESS 0100h 0104h 0108h 010Ch 0110h 0114h 0118h 011Ch 0120h 0124h 0128h 012Ch 0130h 0134h 0138h 013Ch 0140h 0144h 0148h 014Ch 0150h 0154h 0158h 015Ch 0160h 0164h 0168h 016Ch 0170h 0174h 0180h ...
Page 83
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.19.1 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface ...
Page 84
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.19.2 Ethernet MAC Management Counters for RFC2819 RMON RFC2819 RMON EtherStatsEntry Support VARIABE NAME etherStatsIndex etherStatsDataSource etherStatsDropEvents etherStatsOctets etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts etherStatsCRCAlignErrors etherStatsUndersizePkts etherStatsOversizePkts etherStatsFragments etherStatsJabbers etherStatsCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1024to1518Octets etherStatsOwner etherStatsStatus Note that implementations ...
Page 85
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.19.3 Programmable Ethernet Destination Address Filtering In addition to the automatic learning and filtering features described in Section 8.18, the Ethernet MAC has the capability to filter frames by MAC Destination Address. This feature is available at all ...
Page 86
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20 Ethernet Frame Encapsulation The figure below depicts the Layer 1 mapping and Layer 2 protocol encapsulation options available: WAN (PDH Interfaces) 8.20.1 Transmit Packet Processor (Encapsulator) The data from each WAN Group is processed by the Transmit ...
Page 87
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 In HDLC/cHDLC/LAPS(X.86) mode, the inter-frame fill is selectable per WAN group with PP.EMCR.EIIS. If packet processing is disabled, inter-frame padding is not performed. The frame scrambler scrambles the entire frame data stream. Frame scrambling is ...
Page 88
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 immediately after the cHEC bytes when in GFP mode or after the start flag when in HDLC mode. This bit should be set to 1 for X.86, cHDLC and GFP transport. This bit should be equal to 0 ...
Page 89
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20.3 GFP-F Encapsulation and Decapsulation The GFP-F protocol provides a method for encapsulating Ethernet Frames over point-to-point serial links. The device expects a frame or multiframe synchronization signal to provide the byte boundary. This is provided by the ...
Page 90
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 The final two bytes of the TYPE/tHEC field are used to perform header validation. The tHEC calculation is a CRC- 16 operation in which the two byte PLI is multiplied by X Another common representation for this polynomial ...
Page 91
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20.3.1GFP-F NULL When configured for GFP Null operation, no additional header information is required. The Encapsulator’s Tag 1 Insertion function (in PP.ET1DHR and PP.ET1DLR) is available to insert a 4-byte MPLS tag immediately before the Ethernet Destination Address ...
Page 92
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20.3.2GFP-F Linear Extension When configured for GFP Linear Extension mode, an additional header is required. The Encapsultor’s Tag 1 Insertion function (in PP.ET1DHR and PP.ET1DLR, enabled with PP.EMCR.ET1E) is used to insert the 4-byte GFP Extension Header value. ...
Page 93
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 The Encapsulator’s Tag 2 Insertion function (in PP.ET2DHR and PP.ET2DLR) is available to insert a 4-byte VLAN tag immediately after the Source Address (SA). Any existing VLAN tags are “pushed” lower in the frame. The resulting encapsulated frame ...
Page 94
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20.4 X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame for eventual transport on a SONET or SDH network. LAPS provides a byte-synchronous HDLC-like framing structure for encapsulation of Ethernet frames, but is not ...
Page 95
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 The device will encode the MAC Frame with X.86 / LAPS encapsulation on a complete serial stream if configured for X.86 mode in the register PP.EMCR. The device provides the following functions: • 32 bit FCS 43 • ...
Page 96
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20.5 HDLC Encoding and Decoding The HDLC protocol provides a simple method for encapsulating Ethernet Frames over point-to-point serial links. HDLC Encapsulation can be bit or byte synchronous. In byte synchronous mode, byte stuffing is performed. Byte stuffing ...
Page 97
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 8-21. HDCL Encapsulated Frame Format Flag(0x7E) Address (optional) Control (optional) 1st Octet of Protocol (optional) 2nd Octet of Protocol (optional) MPLS TAG (optional) Destination Address (DA) Source Address (SA) VLAN TAG (optional) Q-in-Q VLAN TAG (existing/optional) Length ...
Page 98
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.20.6 cHDLC Encoding And Decoding The cHDLC protocol provides a simple method for encapsulating Ethernet Frames over point-to-point serial links. A Line Header Insertion function (in PP.ELHHR and PP.ELHLR) allows the user to insert Address, Control, and Protocol ...
Page 99
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.21 CIR/CBS Controller The device provides a Committed Information Rate (CIR) / Committed Burst Rate (CBS) provisioning facility. The CIR/CBS can be used to restrict the transport of received MAC data to a specific rate. The CIR will ...
Page 100
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table 8-22. Credit Threshold Settings with Resulting Bandwidths Low-Range CIR Credit CIR Threshold Bandwidth 243 64.04E+3 121 128.07E+3 80 192.90E+3 60 256.15E+3 48 318.88E+3 40 381.10E+3 34 446.43E+3 30 504.03E+3 26 578.70E+3 23 651.04E+3 21 710.23E+3 19 781.25E+3 ...
Page 101
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 9. Applications Information 9.1 Interfacing to Maxim T1/E1 Transceivers The devices in the DS33X162 product family can be seamlessly connected to Maxim T1/E1 transceivers, without the need for additional external components. The diagram below depicts the electrical connections ...
Page 102
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 9-3. Example Functional Timing: DS2155 T1 Transmit-Side Boundary Timing TCLK TCHCLK LSB X MSB TSER TSYNC * Note DS2155 TCLK shown only for comparative purposes. Figure 9-4. Example Functional Timing: DS2155 E1 Receive-Side Boundary Timing RCLK RCHCLK ...
Page 103
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 9.2 Interfacing to Maxim T3/E3 Transceivers The devices in the DS33X162 product family can be seamlessly connected to Maxim T3/E3 transceivers, without the need for additional external components. The diagram below depicts the electrical connections between the devices. ...
Page 104
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Figure 9-8. Example Functional Timing: DS3170 DS3 Receive-Side Boundary Timing RCLKO or RCLKI RSOFO DS3 RGCLK DS3 RSER X1 DS3 RDEN Because the third gapped transmit clock input edge after the transmit sync pulse ...
Page 105
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10. Device Registers Eleven address bits are used address the register space. The register map is shown in Table 10-1. The addressable range is 000h-7FFh. Register address locations are shared across the product family to preserve software compatibility. ...
Page 106
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.1 Register Bit Maps 10.1.1 Global Register Bit Map Table 10-2. Global Register Bit Map A Name B 7 DDR IT WP4 000h GL.IDR REV2 001h - 002h GL.CR1 - 003h - 004h GL.CR2 - 005h - 008h ...
Page 107
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT SU.MAC1RADL MACRA7 040h SU.MAC1RADH MACRA15 MACRA14 MACRA13 MACRA12 MACRA11 MACRA10 041h SU.MAC1RD0 MACRD7 042h SU.MAC1RD1 MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 043h SU.MAC1RD2 MACRD23 MACRD22 MACRD21 MACRD20 MACRD19 MACRD18 MACRD17 MACRD16 ...
Page 108
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT WNVDF 0A0h SU.WEM - 0A1h - 0A2h SU.WEHTP - 0A3h WEHT8 0A4h SU.WEHT WEHT16 0A5h WEDAL8 0A6h SU.WEDAL WEDAL16 WEDAL15 WEDAL14 WEDAL13 WEDAL12 WEDAL11 WEDAL10 0A7h WEDAM8 0A8h SU.WEDAM WEDAM16 WEDAM15 WEDAM14 ...
Page 109
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT LEET15 0CBh LP1MIM 0CCh SU.LP1C - 0CDh LP2MIM 0CEh SU.LP2C - 0CFh - 0D0h SU.LNFC - 0D1h LQXPC8 0D2h SU.LQXPC LQXPC16 LQXPC15 LQXPC14 LQXPC13 LQXPC12 LQXPC11 LQXPC10 0D3h LQTPID8 0D4h SU.LQTPID LQTPID16 ...
Page 110
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT LQ1SA-8 100h AR.LQ1SA - 101h LQ2SA-8 102h AR.LQ2SA - 103h LQ3SA-8 104h AR.LQ3SA - 105h LQ4SA-8 106h AR.LQ4SA - 107h LQ5SA-8 108h AR.LQ5SA - 109h LQ6SA-8 10Ah AR.LQ6SA 10Bh - LQ7SA-8 10Ch ...
Page 111
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT LQ4EA-8 126h AR.LQ4EA - 127h LQ5EA-8 128h AR.LQ5EA - 129h LQ6EA-8 12Ah AR.LQ6EA - 12Bh LQ7EA-8 12Ch AR.LQ7EA - 12Dh LQ8EA-8 12Eh AR.LQ8EA - 12Fh LQ9EA-8 130h AR.LQ9EA - 131h 132h LQ10EA-8 ...
Page 112
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 14Fh WQ9SA-8 WQ9SA-7 WQ9SA-6 WQ9SA-5 WQ9SA-4 WQ9SA-3 WQ9SA-2 WQ9SA-1 150h AR.WQ9SA - 151h 152h WQ10SA-8 AR.WQ10SA 153h - 154h WQ11SA-8 AR.WQ11SA 155h - 156h WQ12SA-8 AR.WQ12SA 157h - 158h WQ13SA-8 AR.WQ13SA ...
Page 113
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT 178h WQ13EA-8 AR.WQ13EA 179h - 17Ah WQ14EA-8 AR.WQ14EA 17Bh - 17Ch WQ15EA-8 AR.WQ15EA 17Dh - 17Eh WQ16EA-8 AR.WQ16EA 17Fh - 180h LIQSA-8 AR.LIQSA 181h - 182h LIQEA-8 AR.LIQEA 183h - 184h LEQSA-8 ...
Page 114
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT 1A1h WQOS-16 1A2h WQOIM-8 AR.WQOIM 1A3h WQOIM-16 1A4h WQNFS-8 AR.WQNFS 1A5h WQNFS-16 WQNFS-15 WQNFS-14 WQNFS-13 WQNFS-12 WQNFS-11 WQNFS-10 1A6h WQNFIM-8 AR.WQNFIM 1A7h WQNFIM-16 WQNFIM-15 WQNFIM-14 WQNFIM-13 WQNFIM-12 WQNFIM-11 WQNFIM-10 WQNFIM-9 1A8h - ...
Page 115
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT ELHD23 242h PP.ELHHR ELHD31 243h ELHD7 244h PP.ELHLR ELHD15 245h ET1D23 246h PP.ET1DHR ET1D31 247h ET1D7 248h PP.ET1DLR ET1D15 249h ET2D23 24Ah PP.ET2DHR ET2D31 24Bh ET2D7 24Ch PP.ET2DLR ET2D15 24Dh 24Eh EEI5 ...
Page 116
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT EOPLE 29Eh PP.ESMLS 29Fh - EOPLEIE 2A0h PP.ESMIE 2A1h - EHFL7 2A6h PP.EHFL 2A7h - EIIS 2C0h PP.EMCR EGCM 2C1h ELHD23 2C2h PP.ELHHR ELHD31 2C3h ELHD7 2C4h PP.ELHLR 2C5h ELHD15 ET1D23 2C6h ...
Page 117
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT DR1E 300h PP.DMCR DGCM 301h D1D7D 302h PP.DA1DR D1D15D 303h D2D7D 304h PP.DA2DR D2D15D 305h D3D7D 306h PP.DA3DR D3D15D 307h D4D7D 308h PP.DA4DR D4D15D 309h D5D7D 30Ah PP.DA5DR 30Bh D5D15D D6D7D 30Ch ...
Page 118
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT DR1E 340h PP.DMCR DGCM 341h D1D7D 342h PP.DA1DR D1D15D 343h D2D7D 344h PP.DA2DR D2D15D 345h D3D7D 346h PP.DA3DR D3D15D 347h D4D7D 348h PP.DA4DR D4D15D 349h D5D7D 34Ah PP.DA5DR 34Bh D5D15D D6D7D 34Ch ...
Page 119
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT DR1E 380h PP.DMCR DGCM 381h D1D7D 382h PP.DA1DR D1D15D 383h D2D7D 384h PP.DA2DR D2D15D 385h D3D7D 386h PP.DA3DR D3D15D 387h D4D7D 388h PP.DA4DR D4D15D 389h D5D7D 38Ah PP.DA5DR 38Bh D5D15D D6D7D 38Ch ...
Page 120
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT DR1E 3C0h PP.DMCR DGCM 3C1h D1D7D 3C2h PP.DA1DR D1D15D 3C3h D2D7D 3C4h PP.DA2DR D2D15D 3C5h D3D7D 3C6h PP.DA3DR D3D15D 3C7h D4D7D 3C8h PP.DA4DR D4D15D 3C9h D5D7D 3CAh PP.DA5DR 3CBh D5D15D D6D7D 3CCh ...
Page 121
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT V4FM1 400h VCAT.TCR1 - 401h TV2MC3 402h VCAT.TCR2 TV4MC3 403h - 406h VCAT.TLCR1 - 407h - 408h VCAT.TLCR2 - 409h V1MST7 40Ah VCAT.TLCR3 V1MST15 40Bh V2MST7 40Ch VCAT.TLCR4 40Dh V2MST15 V3MST7 40Eh ...
Page 122
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 434h VCAT.TCR3 (11) - 435h - 436h VCAT.TCR3 (12) - 437h - 438h VCAT.TCR3 (13) - 439h - 43Ah VCAT.TCR3 (14) - 43Bh - 43Ch VCAT.TCR3 (15) - 43Dh - 43Eh ...
Page 123
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 45Dh - 45Eh VCAT.TLCR8(16) - 45Fh TGID7 480h VCAT.TCR4 (1) TGID15 481h TGID7 482h VCAT.TCR4 (2) TGID15 483h TGID7 484h VCAT.TCR4 (3) TGID15 485h TGID7 486h VCAT.TCR4 (4) TGID15 487h 500h ...
Page 124
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT RFRST 539h RFM 53Ah VCAT.RCR4 (6) RFRST 53Bh RFM 53Ch VCAT.RCR4 (7) RFRST 53Dh RFM 53Eh VCAT.RCR4 (8) RFRST 53Fh RFM 540h VCAT.RCR4 (9) RFRST 541h RFM 542h VCAT.RCR4 (10) RFRST 543h ...
Page 125
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 562h VCAT.RSR1 (10) RVSQ3 563h - 564h VCAT.RSR1 (11) RVSQ3 565h - 566h VCAT.RSR1 (12) RVSQ3 567h - 568h VCAT.RSR1 (13) RVSQ3 569h - 56Ah VCAT.RSR1 (14) RVSQ3 56Bh - 56Ch ...
Page 126
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 58Bh - 58Ch VCAT.RSR2 (15) - 58Dh - 58Eh VCAT.RSR2 (16) - 58Fh - 590h VCAT.RSLSR(1) - 591h - 592h VCAT.RSLSR(2) - 593h - 594h VCAT.RSLSR(3) - 595h - 596h VCAT.RSLSR(4) ...
Page 127
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 5B4h VCAT.RSIE (3) - 5B5h - 5B6h VCAT.RSIE (4) - 5B7h - 5B8h VCAT.RSIE (5) - 5B9h - 5BAh VCAT.RSIE (6) - 5BBh - 5BCh VCAT.RSIE (7) - 5BDh - 5BEh ...
Page 128
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT RGID15 5DDh RGID7 5DEh VCAT.RSR3 (8) RGID15 5DFh RGID7 5E0h VCAT.RSR3 (9) RGID15 5E1h RGID7 5E2h VCAT.RSR3 (10) RGID15 5E3h RGID7 5E4h VCAT.RSR3 (11) RGID15 5E5h RGID7 5E6h VCAT.RSR3 (12) RGID15 5E7h ...
Page 129
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT 660h - LI.TCR (5) - 661h 668h - LI.TCR (6) - 669h 670h - LI.TCR (7) - 671h 678h - LI.TCR (8) - 679h 680h - LI.TCR (9) - 681h 688h - ...
Page 130
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 A Name B 7 DDR IT - 740h LI.RCR1 (1) - 741h - 748h LI.RCR1 (2) - 749h - 750h LI.RCR1 (3) - 751h - 758h LI.RCR1 (4) - 759h - 760h LI.RCR1 (5) - 761h - 768h ...
Page 131
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.1.2 MAC Indirect Register Bit Map Table 10-3. MAC Indirect Register Bit Map DDR AME IT SU.MACCR 0000h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 31:24 23:16 WDD 15:8 GMIIMIIS 7:0 ACST SU.MACFFR ...
Page 132
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT SU.ADDR1H 0048h MADDR1AE 31:24 23:16 - 15:8 MADDR1[47] 7:0 MADDR1[39] SU.ADDR1L 004Ch MADDR1[31] 31:24 23:16 MADDR1[23] 15:8 MADDR1[15] 7:0 MADDR1[7] SU.ADDR2H 0050h MADDR2AE 31:24 23:16 - 15:8 MADDR2[47] 7:0 MADDR2[39] SU.ADDR2L ...
Page 133
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 23:16 - 15:8 MADDR6[47] 7:0 MADDR6[39] SU.ADDR6L 0074h MADDR6[31] 31:24 23:16 MADDR6[23] 15:8 MADDR6[15] 7:0 MADDR6[7] SU.ADDR7H 0078h MADDR7AE 31:24 23:16 - 15:8 MADDR7[47] 7:0 MADDR7[39] SU.ADDR7L 007Ch MADDR7[31] 31:24 23:16 ...
Page 134
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 15:8 MADDR11[47] MADDR11[46] MADDR11[45] MADDR11[44] MADDR11[43] MADDR11[42] MADDR11[41] MADDR11[40] 7:0 MADDR11[39] MADDR11[38] MADDR11[37] MADDR11[36] MADDR11[35] MADDR11[34] MADDR11[33] MADDR11[32] SU.ADDR11L 009Ch MADDR11[31] MADDR11[30] MADDR11[29] MADDR11[28] MADDR11[27] MADDR11[26] MADDR11[25] MADDR11[24] 31:24 23:16 MADDR11[23] ...
Page 135
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 7:0 - SU.ANSR 00C4h - 31:24 23:16 - 15:8 - 7:0 - SU.LSR 00D8h - 31:24 23:16 - 15:8 - 7:0 - SU.MMCCTRL 0100h - 31:24 23:16 - 15:8 - 7:0 ...
Page 136
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 15:8 TXGBFC[15] TXGBFC[14] TXGBFC[13] TXGBFC[12] TXGBFC[11] TXGBFC[10] TXGBFC[9] 7:0 TXGBFC[7] SU.TXGMFC 0120h TXGMFC[31] 31:24 23:16 TXGMFC[23] 15:8 TXGMFC[15] 7:0 TXGMFC[7] TXGMFC[6] TXGMFC[5] TXGMFC[4] TXGMFC[3] TXGMFC[2] TXGMFC[1] TXGMFC[0] SU.TX0_64 0124h TX0_64[31] 31:24 ...
Page 137
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT SU.TXUFE 0148h TXUFE[31] 31:24 23:16 TXUFE[23] 15:8 TXUFE[15] 7:0 TXUFE[7] SU.TXSNGLCL 014Ch TXSNGLCL[31] 31:24 23:16 TXSNGLCL[23] 15:8 TXSNGLCL[15] 7:0 TXSNGLCL[7] SU.TXMLTICL 0150h TXMLTICL[31] 31:24 23:16 TXMLTICL[23] 15:8 TXMLTICL[15] 7:0 TXMLTICL[7] SU.TXDFRD ...
Page 138
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 15:8 TXPAUSE[15] TXPAUSE[14] TXPAUSE[13] TXPAUSE[12] TXPAUSE[11] TXPAUSE[10] 7:0 TXPAUSE[7] SU.TXVLANF 0174h TXVLANF[31] TXVLANF[30] TXVLANF[29] TXVLANF[28] TXVLANF[27] TXVLANF[26] TXVLANF[25] TXVLANF[24] 31:24 23:16 TXVLANF[23] TXVLANF[22] TXVLANF[21] TXVLANF[20] TXVLANF[19] TXVLANF[18] TXVLANF[17] TXVLANF[16] 15:8 TXVLANF[15] ...
Page 139
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 23:16 RXALGN[23] RXALGN[22] RXALGN[21] RXALGN[20] RXALGN[19] RXALGN[18] RXALGN[17] RXALGN[16] 15:8 RXALGN[15] RXALGN[14] RXALGN[13] RXALGN[12] RXALGN[11] RXALGN[10] RXALGN[9] RXALGN[8] 7:0 RXALGN[7] RXALGN[6] SU.RXRUNT RXRUNT[31 019Ch 31:24 ] 23:16 RXRUNT[23 ] 15:8 RXRUNT[15 ...
Page 140
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 DDR AME IT 23:16 RX1K_MAX[23] 15:8 RX1K_MAX[15] 7:0 RX1K_MAX[7] SU.RXUFC 01C4h RXUFC[31] 31:24 23:16 RXUFC[23] 15:8 RXUFC[15] 7:0 RXUFC[7] SU.RXLNERR 01C8h RXLNERR[31] RXLNERR[30] RXLNERR[29] RXLNERR[28] RXLNERR[27] RXLNERR[26] RXLNERR[25] RXLNERR[24] 31:24 23:16 RXLNERR[23] RXLNERR[22] RXLNERR[21] ...
Page 141
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.2 Global Register Definitions Note that although most registers are defined as 16-bit registers, the constituent bytes are accessed through the parallel or SPI interfaces one byte at a time. Individual address locations are defined for each byte. ...
Page 142
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 003h Default 0 0 Bit 7 Bit 6 002h Default 0 0 Bit 13: LAN Port 2 Speed Selection (P2SPD 10Mbps operation ...
Page 143
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 005h Default 0 0 Bit 7 Bit 6 004h Default 0 0 Bit 3: Interrupt Mode (INTM) When this bit is set to 1, ...
Page 144
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 009h: MICIS DECIS4 Default 0 0 Bit 7 Bit 6 008h: - BUFIS Default 0 0 Bit 15: Microprocessor Interrupt Status (MICIS) This bit is set if the ...
Page 145
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 00Bh: MICIE DECIE4 Default 0 0 Bit 7 Bit 6 00Ah: - BUFIE Default 0 0 Bit 15: Microport Interrupt Enable (MICIE) When this bit is set to ...
Page 146
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 00Dh Default 0 0 Bit 7 Bit 6 00Ch Default 0 0 Bit 11: DPLL Lock (DLOCK) This bit is set ...
Page 147
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.2.1 Microport Registers Register Name: Register Description: Register Address: Bit 15 Bit 14 021h Default 0 0 Bit 7 Bit 6 020h Default 0 0 Bits 0-1: FIFO[1:0] FIFO Selection These bits select which ...
Page 148
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 025h Default 0 0 Bit 7 Bit 6 024h: LILEN7 LILEN6 Default 0 0 Bits 0-11: LAN Insertion Frame Length (LILEN[11:0])These bits determine the number of ...
Page 149
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 02Bh Default 0 0 Bit 7 Bit 6 02Ah Default 0 0 Bit 3: LAN Extraction Available (LANEA) Set when the LAN Extraction FIFO ...
Page 150
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 02Fh Default 0 0 Bit 7 Bit 6 02Eh Default 0 0 Bit 3: LAN Extraction Available Interrupt Enable (LANEAIE) This bit enables LANEAL ...
Page 151
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 033h Default 0 0 Bit 7 Bit 6 032h: RPKT7 RPKT6 Default 0 0 Bits 0-7: Packet Read Byte (RPKT[7:0 Extraction FIFO is selected, ...
Page 152
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.2.2 MAC 1 Interface Access Registers Register Name: Register Description: Register Address: Bit 7 Bit 6 040h: MACRA7 MACRA6 Default 0 0 Bits 0 – 7: MAC Read Address (MACRA0-7) - Low byte of the MAC address. Used ...
Page 153
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 7 Bit 6 043h: MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 Default 0 0 Bits MAC Read Data 1 (MACRD8-15) - One of four bytes of data read from ...
Page 154
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 7 Bit 6 047h: MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08 Default 0 0 Bits 0 – 7: MAC Write Data 1 (MACWD8-15) - One of four bytes of data ...
Page 155
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 7 Bit 6 04Bh: MACAW15 MACAW14 MACAW13 MACAW12 MACAW11 MACAW10 Default 0 0 Bits 0 – 7: MAC Write Address (MACAW8-15) - High byte of the MAC address. Used only for ...
Page 156
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.2.3 MAC 2 Interface Access Registers Register Name: Register Description: Register Address: Bit 7 Bit 6 060h: MACRA7 MACRA6 Default 0 0 Bits 0 – 7: MAC Read Address (MACRA0-7) - Low byte of the MAC address. Used ...
Page 157
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 7 Bit 6 063h: MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 Default 0 0 Bits MAC Read Data 1 (MACRD8-15) - One of four bytes of data read from ...
Page 158
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 7 Bit 6 067h: MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08 Default 0 0 Bits 0 – 7: MAC Write Data 1 (MACWD8-15) - One of four bytes of data ...
Page 159
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 7 Bit 6 06Bh: MACAW15 MACAW14 MACAW13 MACAW12 MACAW11 MACAW10 Default 0 0 Bits 0 – 7: MAC Write Address (MACAW8-15) - High byte of the MAC address. Used only for ...
Page 160
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.2.4 VLAN Control Registers Register Name: Register Description: Register Address: Bit 15 Bit 14 081h Default 0 0 Bit 7 Bit 6 080h Default 0 0 This register is used to control the VLAN ...
Page 161
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 085h Default 0 0 Bit 7 Bit 6 084h Default 0 0 Whenever a write is performed to this configuration register address the data ...
Page 162
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 087h Default 0 0 Bit 7 Bit 6 086h Default 0 0 Whenever a read operation is performed on this configuration register, the data ...
Page 163
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 089h Default 0 0 Bit 7 Bit 6 088h: VTSA8 VTSA7 Default 0 0 Bit 12: VLAN Table Initialization Status (VTIS): This bit is set to ...
Page 164
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.3 Ethernet Interface Registers The Ethernet Interface registers are used to configure GMII/MII/RMII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers ...
Page 165
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Bits 4-5: WAN Extract Decap Source (WEDS[2:1 WAN Extract performed on the data stream from Decapsulator 1 (WAN Group 1 WAN Extract performed on the data stream from ...
Page 166
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0A3h Default 0 0 Bit 7 Bit 6 0A2h Default 0 0 Bit 4: WAN Extract Header Trap High Byte (WEHTH). This value indicates ...
Page 167
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0A5h: WEHT16 WEHT15 Default 0 0 Bit 7 Bit 6 0A4h: WEHT8 WEHT7 Default 0 0 Bits 0-15: WAN Header Trap (WEHT [16:1]) This value provides the first ...
Page 168
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0ABh: WEDAH16 WEDAH15 Default 0 0 Bit 7 Bit 6 0AAh: WEDAH8 WEDAH7 Default 0 0 Bits 0-15: WAN Extract Destination Address High (WEDAH [16:1]) This value provides ...
Page 169
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0AFh: WEET16 WEET15 Default 0 0 Bit 7 Bit 6 0AEh: WEET8 WEET7 Default 0 0 Bits 0-15: WAN Extract Ethernet Type (WEET [16:1]). This value defines the ...
Page 170
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0B5h Default 0 0 Bit 7 Bit 6 0B4h Default 0 0 Bit 0: WAN Extract Overflow Status overflow events have ...
Page 171
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0B7h Default 0 0 Bit 7 Bit 6 0B6h Default 0 0 Bit 11: LAN Port #2 - SRAM Queue Reset (LP2R ...
Page 172
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0B9h Default 0 0 Bit 7 Bit 6 0B8h Default 0 0 Bit 0: WAN Extract Overflow Interrupt Mask 0 = WEOS will cause ...
Page 173
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0BBh: LTED LTJTO Default 0 0 Bit 7 Bit 6 0BAh: - LTCC3 Default 0 0 NOTE: This is a real-time status register. Usefulness is limited to single ...
Page 174
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0BDh: LTED LTJTO Default 0 0 Bit 7 Bit 6 0BCh: - LTCC3 Default 0 0 NOTE: This is a real-time status register. Usefulness is limited to single ...
Page 175
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.3.2 Receive LAN Register Definitions Register Name: Register Description: Register Address: Bit 15 Bit 14 0C1h Default 0 0 Bit 7 Bit 6 0C0h Default 0 0 This register determines which set of LAN ...
Page 176
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0C3h: LEDAL15 LEDAL14 Default 0 0 Bit 7 Bit 6 0C2h: LEDAL7 LEDAL6 Default 0 0 Bits 0-15: LAN Extract Destination Address Low (LEDAL[16:1]). This value provides the ...
Page 177
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0C7h: LEDAH15 LEDAH14 Default 0 0 Bit 7 Bit 6 0C6h: LEDAH7 LEDAH6 Default 0 0 Bits 0-15: LAN Extract Destination Address High (LEDAH[16:1]) This value provides the ...
Page 178
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0CBh: LEET15 LEET14 Default 0 0 Bit 7 Bit 6 0CAh: LEET7 LEET6 Default 0 0 Bits 0-15: LAN Extract Ethernet Type (LEET[16:1]). This value defines the 2-byte ...
Page 179
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0CFh Default 0 0 Bit 7 Bit 6 0CEh: LP2MIM LP2QOM Default 0 0 Bit 7: LAN Port 2 MAC Interrupt Mask control (LP2MIM ...
Page 180
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0D1h Default 0 0 Bit 7 Bit 6 0D0h Default 0 0 Bit 4-5: LAN No Priority Tag Detected Forwarding (LNPDF[2:1]). Enabled for each ...
Page 181
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0D5h: LQTPID16 LQTPID15 Default 0 0 Bit 7 Bit 6 0D4h: LQTPID8 LQTPID7 Default 0 0 Bits 0-15: LAN Q-in-Q Tag Protocol ID (LQTPID [16:1]) This register specifies ...
Page 182
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0D9h Default 0 0 Bit 7 Bit 6 0D8h: MPL8 MPL7 Default 1 1 Bits 0-13: Maximum Packet Length (MPL [14:1]) Maximum frame length, in bytes. ...
Page 183
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0DBh: CBSS - Default 0 0 Bit 7 Bit 6 0DAh: L1PCT8 L1PCT7 Default 0 0 LAN 1 Policing Parameters . This register determines the Policing function setting ...
Page 184
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0DDh: CBSS - Default 0 0 Bit 7 Bit 6 0DCh: L2PCT8 L2PCT7 Default 0 0 LAN 2 Policing Parameters. This register determines the Policing function setting for ...
Page 185
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0DFh Default 0 0 Bit 7 Bit 6 0DEh Default 0 0 Priority Table Control This register is used to initialize and specify the ...
Page 186
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0E1h Default 0 0 Bit 7 Bit 6 0E0h: - PTPAA Default 0 0 Bit 6: Priority Table Port Access Address (PTPAA). This bit is an ...
Page 187
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 0E5h Default 0 0 Bit 7 Bit 6 0E4h Default 0 0 Bits 0-1: LAN Priority Queue Forwarding (LPQFR[2:1 The value of ...
Page 188
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.3.3 Bridge Filter Registers Register Name: Register Description: Register Address: Bit 15 Bit 14 0E9h Default 0 0 Bit 7 Bit 6 0E8h: BFAP8 BFAP7 Default 0 0 Bit 10: Bridge Filter Table Reset (BFTR). When ...
Page 189
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 10.4 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to ...
Page 190
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 105h Default 0 0 Bit 7 Bit 6 104h: LQ3SA-8 LQ3SA-7 Default 0 0 Bit 10: LAN Queue 3 Queue Pointer Reset reset ...
Page 191
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 109h Default 0 0 Bit 7 Bit 6 108h: LQ5SA-8 LQ5SA-7 Default 0 0 Bit 10: LAN Queue 5 Queue Pointer Reset reset ...
Page 192
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 10Dh Default 0 0 Bit 7 Bit 6 10Ch: LQ7SA-8 LQ7SA-7 Default 0 0 Bit 10: LAN Queue 7 Queue Pointer Reset reset ...
Page 193
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 111h Default 0 0 Bit 7 Bit 6 110h: Bit 7 Bit 6 Default 0 0 Bit 10: LAN Queue 9 Queue Pointer Reset ...
Page 194
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 115h Default 0 0 Bit 7 Bit 6 114h: LQ11SA-8 LQ11SA-7 Default 0 0 Bit 10: LAN Queue 11 Queue Pointer Reset reset ...
Page 195
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 119h Default 0 0 Bit 7 Bit 6 118h: LQ13SA-8 LQ13SA-7 Default 0 0 Bit 10: LAN Queue 13 Queue Pointer Reset reset ...
Page 196
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 11Dh Default 0 0 Bit 7 Bit 6 11Ch: LQ15SA-8 LQ15SA-7 Default 0 0 Bit 10: LAN Queue 15 Queue Pointer Reset reset ...
Page 197
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 121h Default 0 0 Bit 7 Bit 6 120h: LQ1EA-8 LQ1EA-7 Default 0 0 Bits 0-9: LAN Queue 1 End Address [10-1] This register specifies the ...
Page 198
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Bit 15 Bit 14 127h Default 0 0 Bit 7 Bit 6 LQ4EA-8 LQ4EA-7 126h: Default 0 0 Bits 0-9: LAN Queue 4 End Address [10-1] This register specifies the End Address for the LAN Queue ...
Page 199
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 12Dh Default 0 0 Bit 7 Bit 6 12Ch: LQ7EA-8 LQ7EA-7 Default 0 0 Bits 0-9: LAN Queue 7 End Address [10-1] This register specifies the ...
Page 200
DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Register Name: Register Description: Register Address: Bit 15 Bit 14 133h Default 0 0 Bit 7 Bit 6 132h: LQ10EA-8 LQ10EA-7 Default 0 0 Bits 0-9: LAN Queue 10 End Address [10-1]. This register specifies the ...