DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 85
![IC MAPPER ETHERNET 100CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS33ZH11+
Manufacturer Part Number
DS33ZH11+
Description
IC MAPPER ETHERNET 100CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS33Z11.pdf
(172 pages)
Specifications of DS33ZH11+
Applications
Data Transport
Interface
Serial
Voltage - Supply
1.8V, 2.5V, 3.3V
Package / Case
100-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with a
formula of x
BERT generates a series of bits by iteration of the formula.
Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and
PTF[0:4], and BSP[0:31]. When 1, the pattern generator configuration is forced to a QRSS pattern with a
generating polynomial of x
output bits are all zero.
Bit 5: Pattern Type Select (PTS) When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]) These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n. The values possible are
outlined in Section 8.15.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]) These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y. The
values possible are outlined in Section 8.15.
n
+ x
7
0
7
0
-
-
y
+ 1. The initial value for x (the seed) is placed in the BSPB (bert seed/pattern) register. The
QRSS
20
6
0
6
0
-
+ x
17
BPCLR
BERT Pattern Configuration Low Register
82h
BPCHR
BERT Pattern Configuration High Register
83h
+ 1. The output of the pattern generator is forced to one if the next fourteen
PTS
5
0
5
0
-
85 of 172
PTF4
PLF4
4
0
4
0
PLF3
PTF3
3
0
3
0
PTF2
PLF2
2
0
2
0
PLF1
PTF1
1
0
1
0
PLF0
PTF0
0
0
0
0
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