DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 113

• Manufacturer Part Number: DS33ZH11+
• Description: IC MAPPER ETHERNET 100CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33ZH11+

• Applications: Data Transport
• Interface: Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 100-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 – 7: Transmit Queue High Threshold (TQHT[0:7]) The transmit queue high threshold for the connection,
in increments of 32 packets of 2048 bytes each. The value of this register is multiplied by 32 * 2048 bytes to
determine the byte location of the threshold. Note that the transmit queue is for data that was received from the
Serial Interface to be sent to the Ethernet Interface.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark
interrupt is enabled for TFOVFLS.
Bit 2: Transmit Queue Overflow for Connection Interrupt Enable (TQOVFIE) If this bit is set, the watermark
interrupt is enabled for TQOVFLS.
Bit 1: Transmit Queue for Connection High Threshold Interrupt Enable (TQHTIE) If this bit is set, the
watermark interrupt is enabled for TQHTS.
Bit 0: Transmit Queue for Connection Low Threshold Interrupt Enable (TQLTIE) If this bit is set, the
watermark interrupt is enabled for TQLTS.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: Transmit Queue FIFO Overflowed Latched Status (TFOVFLS) This bit is set if the transmit queue FIFO
has overflowed. This register is cleared after a read. This FIFO is for data to be transmitted from the HDLC to be
sent to the SDRAM.
Bit 2: Transmit Queue Overflow Latched Status (TQOVFLS) This bit is set if the transmit queue has
overflowed. This register is cleared after a read.
Bit 1: Transmit Queue for Connection Exceeded High Threshold Latched Status (TQHTLS) This bit is set if
the transmit queue crosses the High Watermark. This register is cleared after a read.
Bit 0: Transmit Queue for Connection Exceeded Low Threshold Latched Status (TQLTLS) This bit is set if
the transmit queue crosses the Low Watermark. This register is cleared after a read.
TQHT7
7
0
7
0
7
-
-
-
TQHT6
6
0
6
0
6
-
-
-
LI.TQHT
Serial Interface Transmit Queue High Threshold (Watermark)
125h
LI.TQTIE
Serial Interface Transmit Queue Cross Threshold Interrupt Enable
126h
LI.TQCTLS
Serial Interface Transmit Queue Cross Threshold Latched Status
127h
TQHT5
5
0
5
0
5
-
-
-
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TQHT4
4
0
4
0
4
-
-
-
TFOVFLS
TFOVFIE
TQHT3
3
0
3
0
3
-
TQOVFLS
TQOVFIE
TQHT2
2
0
2
0
2
-
TQHTLS
TQHTIE
TQHT1
1
0
1
0
1
-
TQLTLS
TQLTIE
TQHT0
0
0
0
0
0
-