DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet
DS33ZH11+
Specifications of DS33ZH11+
Related parts for DS33ZH11+
DS33ZH11+ Summary of contents
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GENERAL DESCRIPTION The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a PDH/TDM data stream. The serial link supports bidirectional- synchronous interconnect up to 52Mbps over xDSL, T1/E1/J1, ...
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DESCRIPTION..................................................................................................................................7 2 FEATURE HIGHLIGHTS ..................................................................................................................8 2.1 G .......................................................................................................................................................8 ENERAL 2 .........................................................................................................................................8 ERIAL NTERFACE 2.3 HDLC ...........................................................................................................................................................8 2 OMMITTED NFORMATION 2.5 X.86 S ..............................................................................................................................................8 UPPORT 2.6 SDRAM I .......................................................................................................................................9 NTERFACE 2.7 MAC I ............................................................................................................................................9 NTERFACE 2.8 ...
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Pattern Monitoring...............................................................................................................................52 8.15.4 Pattern Generation..............................................................................................................................52 8. RANSMIT ACKET ROCESSOR 8. ECEIVE ACKET ROCESSOR 8.18 X. NCODING AND ECODING 8. OMMITTED NFORMATION 8. ........................................................................................................................................62 ARDWARE ODE 9 DEVICE ...
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IDCODE ............................................................................................................................................167 12.3 JTAG ID C ........................................................................................................................................168 ODES 12 .......................................................................................................................................168 EST EGISTERS 12 OUNDARY CAN EGISTER 12 .....................................................................................................................................168 YPASS EGISTER 12 DENTIFICATION EGISTER 12.8 JTAG F T UNCTIONAL IMING 13 ...
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Figure 3-1 Ethernet to WAN Extension (No Framing)............................................................................................. 11 Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU) ........................................................................... 12 Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing................................................................................... 12 Figure 3-4 Ethernet over DSL.................................................................................................................................. 13 Figure 3-5 Copper ...
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Table 2-1 T1-Related Telecommunications Specifications ..................................................................................... 10 Table 7-1 Detailed Pin Descriptions ........................................................................................................................ 17 Table 8-1 Clocking Options for the Ethernet Interface ............................................................................................ 31 Table 8-2 Reset Functions ...................................................................................................................................... 34 Table 8-3 Registers Related to Connections and Queues...................................................................................... 39 Table ...
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DESCRIPTION The DS33Z11 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate controller ...
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FEATURE HIGHLIGHTS 2.1 General • 169-pin CSBGA package (DS33Z11) • 100-pin CSBGA package for hardware/SPI modes only (DS33ZH11) • 1.8V supply with 3.3V tolerant inputs and outputs • IEEE 1149.1 JTAG boundary scan • Software access to device ID ...
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SDRAM Interface • Interface for 128 Mb, 32-bit wide SDRAM • SDRAM Interface speed up to 100 MHz • Auto refresh timing • Automatic precharge • Master clock provided to the SDRAM • No external components required for SDRAM ...
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Specifications Compliance The DS33Z11 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33Z11. Table 2-1 T1-Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications RFC1662—PPP in HDLC-like ...
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APPLICATIONS The DS33Z11 is designed for use in the following applications: Transparent LAN Service LAN Extension Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4 Refer also to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge for ...
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Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU) HDLC Serial Stream T1 Framer/LIU DS21Q55 DS26528 Port Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing HDLC Serial Streams T3 Framer/LIU DS3154 DS3144 Port RMII, MII 10 Base T ...
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Figure 3-4 Ethernet over DSL HDLC Serial Streams DSL Figure 3-5 Copper to Fiber Connection HDLC Serial Streams Optical I/F Fiber & Phy connector RMII, MII 10 Base T 100 Base T DS33Z11 Clock Sources SDRAM RMII MII DS33Z11 Clock ...
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ACRONYMS AND GLOSSARY • BERT: Bit Error-Rate Tester • DCE: Data Communication Interface • DTE: Data Terminating Interface • FCS: Frame Check Sequence • HDLC: High-Level Data Link Control • MAC: Media Access Control • MII: Media Independent Interface ...
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MAJOR OPERATING MODES The DS33Z11 has three major modes of operation: microprocessor controlled, EEPROM initialized, and Hardware mode. Microprocessor control is possible through the 8-bit parallel control port. More information on microprocessor control is available in Section 8.1. EEPROM ...
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BLOCK DIAGRAMS Figure 6-1 Detailed Block Diagram Microport TSER HDLC TCLKI1 + Serial Line 1 CIR Interface RCLKI1 RSER X.86 JTAG Eprom SPI_SCLK (max 8.33Mhz) Buffer Dev Div by 1,2,4,10 Output clocks: 50,25 Mhz,2.5 Mhz Arbiter SDRAM Output Clocks ...
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PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. JTAG pins are not available on the Hardware mode/SPI-only DS33ZH11 (10mm CSBGA) ...
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PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) RDEN/ H2 RBSYNC REF_CLK D13 REF_CLKO E13 TX_CLK A8 PIN # TYPE 1 Receive Data Enable: The receive data enable is programmable to block the receive data. The RDEN must be coincident ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) TX_EN E10 TXD[0] B9 TXD[1] C9 TXD[2] D9 TXD[3] E9 RX_CLK A10 B10 RXD[0] B11 RXD[1] C11 D10 RXD[2] D11 RXD[3] A11 C10 RX_DV D10 A10 RX_CRS/ C8 CRS_DV TYPE ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) RX_ERR B12 COL_DET B13 MDC C12 MDIO C13 Potential future A0/BREO A1 revision to add on ball A5 Potential future A1/SCD B1 revision to add on ball D8 TYPE 1 ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) Potential future A2/X86ED A2 revision to add on ball D0/MOSI A5 D1/MISO A6 D2/SPICK A7 ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100 — — SPI_CS B8 B5 CKPHA F6 — — RD/DS E1 — WR/RW E2 — INT F3 — RST D8 C1 TYPE 1 Data ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) HWMODE D5 MODEC[0] D6 MODEC[1] D7 DCEDTES A13 RMIIMIIS C4 FULLDS A9 H10S B10 TYPE 1 Hardware Mode: Connect to V Hardware Mode. MODEC[1:0] determines the default A3 I hardware ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) AFCS C10 SDATA[0] M1 SDATA[1] L2 SDATA[2] N1 SDATA[3] M2 SDATA[4] N2 SDATA[5] N4 SDATA[6] N3 SDATA[7] L4 SDATA[8] J3 SDATA[9] M3 SDATA[10] H3 SDATA[11] J1 SDATA[12] J2 SDATA[13] K1 ...
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PIN # DS33ZH1 DS33Z11 NAME CSBGA (169) BGA(100) SDA[6] L9 SDA[7] L5 SDA[8] M5 SDA[9] M7 SDA[10] M8 SDA[11] N8 SBA[0] M6 SBA[1] N7 SRAS K6 SCAS H4 SWE M4 SDMASK[0] N6 SDMASK[1] G4 SDMASK[2] M10 SDMASK[3] M9 SDCLKO N5 ...
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PIN # PIN # DS33ZH1 DS33Z11 NAME 1 CSBGA (169) BGA(100) JTRST E6 — JTCLK D4 — JTDO E5 — JTDI E4 — JTMS F7 — G5–G10, A7, D4– V DD3.3 H5–H10 D8, H10 D2, D3, D12, E3, E11, E12, ...
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Figure 7-1 DS33Z11 169-Ball CSBGA Pinout RMIIMIIS D VSS VDD1.8 VDD1.8 JTCLK E RD/DS WR/RW VDD1.8 JTDI F TCLKI TSER INT VDD1.8 ...
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Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only VDD1.8 TSER HWMODE B TCLKI RCLKI RSER C RST SDATA10 SDATA7 D SDATA13 SDATA14 SDATA8 E SDATA15 SDATA9 SDMASK1 F SDATA11 SDATA1 SDMASK0 G SDATA12 ...
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FUNCTIONAL DESCRIPTION The DS33Z11 provides interconnection and mapping functionality between Ethernet Packet Systems and WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, and T3/E3. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate ...
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Read-Write/Data Strobe Modes The processor interface can operate in either read-write strobe mode or data strobe mode. When MODEC[1: and HWMODE pin = 0 the read-write strobe mode is enabled and a negative pulse on RD performs ...
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CLOCK STRUCTURE The DS33Z11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKI) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be continuous or gapped. ...
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Figure 8-1 Clocking for the DS33Z11 TSER HDLC TCLKI1 + Serial Line 1 Interface RCLKI1 RSER X.86 JTAG SPI_SCLK (max 8.33Mhz) Microport CIR Arbiter SDRAM Interface SDRAM 32 of 172 Eprom Mhz Oscillator Buffer Dev REF_CLKI Div ...
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Serial Interface Clock Modes The Serial Interface timing is determined by the line clocks. Both the transmit and receive clocks (TCLKI and RCLKI) are inputs, and can be gapped. 8.3.2 Ethernet Interface Clock Modes The Ethernet PHY interface has ...
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Resets and Low Power Modes The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset signal resets the status and control registers on the chip (except the resets all ...
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Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the device by pulling the RST pin low or by using the software reset bits outlined in Section 8.4. Clear ...
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Device Interrupts Figure 8-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global ...
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Figure 8-2 Device Interrupt Information Flow Diagram Receive FCS Errored Packet Receive Aborted Packet Receive Invalid Packet Detected Receive Small Packet Detected Receive Large Packet Detected Receive FCS Errored Packet Count Receive Aborted Packet Count Receive Size Violation Packet Count ...
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Serial Interface The Serial (WAN) interface supports time-division multiplexed, serial data input and output Mbps. The Serial interface receives and transmits encapsulated Ethernet packets. The Serial Interface block consists of the physical serial port and HDLC ...
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It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure ...
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Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33Z11 allows for optional flow control based on the queue high watermark or through host processor intervention. There ...
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Full-Duplex Flow Control In the software mode automatic flow control is enabled by default. The host processor can disable this functionality with SU.GCR.ATFLOW. In hardware mode, the user must apply a logic high level to the AFCS pin to ...
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Figure 8-3 Flow Control Using Pause Control Frame Receive Queue Growth 8.12.2 Half Duplex Flow control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of ...
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ETHERNET Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100 Mbps MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains 7 signals with a reference ...
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The MAC circuitry generates a frame status for every frame that is received. This real time status can be read by SU.RFSB0 to SU.RFSB3. Note the frame status is the “real time” status and hence the value will change as ...
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DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can ...
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Figure 8-6 DS33Z11 Configured as a DCE in MII Mode WAN Arbiter 8.14 Ethernet MAC Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the SU.MACWD0-3 registers to be written with 4 bytes ...
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Table 8-6 MAC Control Registers Address 0000h-0003h 0004h-0007h 0008h-000Bh 0014h-0017h 0018h-001Bh 001Ch-001Fh 0100h-0103h Table 8-7 MAC Status Registers Address 0200h-0203h 0204h-0207h 0300h-0303h 0308h-030Bh 030Ch-030Fh 0334h-0337h 0338h-033Bh Register Register Description MAC Control Register. This register is used for programming full duplex, ...
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MII Mode Options The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section ...
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PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of ...
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BERT The BERT can be used for generation and detection of BERT patterns. The BERT is a software programmable test pattern generator and monitor capable of meeting most error performance requirements for digital transmission equipment. The following restrictions are ...
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Figure 8-9 PRBS Synchronization State Diagram Sync 1 bit error Verify 32 bits loaded 8.15.2 Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each ...
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Figure 8-10 Repetitive Pattern Synchronization State Diagram Sync 1 bit error Verify Pattern Matches 8.15.3 Pattern Monitoring Pattern monitoring monitors the incoming data stream for Out Of Synchronization (OOS) condition, bit errors, and counts the incoming bits. An OOS condition ...
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Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream is ...
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Packet scrambling is programmable. Note in Hardware Mode, the scrambling is controlled by A1/SD. Once all packet processing has been completed serial data stream is passed on to the Transmit ...
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FCS error monitoring checks the FCS and aborts errored packets FCS error is detected, the FCS errored packet count is incremented and the packet is marked with an aborted indication FCS error is not detected, the ...
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Figure 8-11 HDLC Encapsulation of MAC Frame Flag(0x7E) Destination Adrs(DA) Source Adrs(SA) Length/Type MAC Client Data PAD FCS for MAC FCS for HDLC Flag(0x7E) MSB Number of Bytes 46-1500 LSB ...
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X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides HDLC type framing structure for encapsulation of Ethernet frames. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. ...
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Figure 8-13 X.86 Encapsulation of the MAC field Flag(0x7E) Address(0x04) Control(0x03) 1st Octect of SAPI(0xfe) 2nd Octect of SAPI(0x01) Destination Adrs(DA) Source Adrs(SA) Length/Type MAC Client Data PAD FCS for MAC FCS for LAPS Flag(0x7E) MSB The DS33Z11 will encode ...
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The X86 received frame is aborted if: • If 7D,7E is detected. This is an abort packet sequence in X.86 • Invalid FCS is detected • The received frame has less than 6 octets • Control, SAPI and address field ...
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Committed Information Rate Controller The DS33Z11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC data to a programmable rate. This is shown in MAC to Transmit HDLC. This can be used ...
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Figure 8-14 CIR in the WAN Transmit Path TSER HDLC TCLKI1 + Serial Line 1 Interface RCLKI1 X.86 RSER SPI_SCLK (max 8.33Mhz) CIR Arbiter SDRAM Interface SDRAM 61 of 172 Eprom Mhz Oscillator Buffer Dev REF_CLK Div ...
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Hardware Mode The hardware mode settings are provided for users who do not want to utilize a Microprocessor or EEPROM. The hardware mode default queue sizes and watermark thresholds can be selected for various line rates using the MODEC ...
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Table 8-9 Specific Functional Default Values for Hardware Mode Functional Block Register Reference Global Connection between Serial and GL.CON1 Ethernet Interfaces Serial Data Transmit Serial Interface LI.TSLCR Configuration Serial Interface Reset and LI.RSTPD Power-down Transmit FCS LI.TPPCL Transmit Inter Frame ...
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Functional Block Register Reference Queue Size and thresholds Transmit Queue Size AR.TQSC1 AR.TQSC1 Transmit Queue High Threshold LI.TQHT LI.TQHT Transmit Queue Low Threshold LI.TQLT LI.TQLT Receive Queue Size AR.RQSC1 AR.RQSC1 Receive Queue Low Threshold SU.RQLT SU.RQLT Receive Queue High Threshold ...
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Table 8-10 Hardware Mode Pins PIN HWMODE MODEC[1:0] RMIIMIIS DCEDTES FULLDS A2/X86ED A1/SCD A0/BREO HARDWARE MODE FUNCTION 0 = Hardware Mode disabled Hardware Mode enabled. Select the hardware mode default settings MII Operation RMII ...
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DEVICE REGISTERS Ten address lines are used to address the register space. shown in. The addressable range for the device is 0000h to 08FFh. Each register section is 64 bytes deep. Global Registers are preserved for software compatibility with ...
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Register Bit Maps Table 9-2, Table 9-3, Table 9-4, that are reserved are noted with a single dash “-“. All registers not listed are reserved and should be initialized with a value of 00h for proper operation, unless otherwise ...
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Arbiter Register Bit Map Table 9-3 Arbiter Register Bit Map DDR AME IT 40h AR.RQSC1 RQSC7 41h AR.TQSC1 TQSC7 9.1.3 BERT Register Bit Map Table 9-4 BERT Register Bit Map DDR ...
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Serial Interface Register Bit Map Table 9-5 Serial Interface Register Bit Map DDR AME IT 0C0h LI.TSLCR - 0C1h LI.RSTPD - 0C2h LI.LPBK - 0C3h - Reserved 0C4h - LI.TPPCL 0C5h LI.TIFGC TIFG7 0C6h LI.TEPLC ...
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DDR AME IT 113h - Reserved 114h LI.RSPCB0 RSPC7 115h LI.RSPCB1 RSPC15 116h LI.RSPCB2 RSPC23 118h LI.RBC0 RBC7 119h LI.RBC1 RBC15 11Ah RBC23 LI.RBC2 11Bh LI.RBC3 RBC31 11Ch LI.RAC0 REBC7 11Dh LI.RAC1 REBC15 11Eh LI.RAC2 REBC23 ...
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Ethernet Interface Register Bit Map Table 9-6 Ethernet Interface Register Bit Map DDR AME IT 140h SU.MACRADL MACRA7 141h SU.MACRADH MACRA15 142h SU.MACRD0 MACRD7 143h SU.MACRD1 MACRD15 144h MACRD23 SU.MACRD2 145h MACRD31 SU.MACRD3 146h SU.MACWD0 ...
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MAC Register Bit Map Table 9-7 MAC Indirect Register Bit Map DDR AME IT SU.MACCR 0000h Reserved 31:24 0001h 23:16 DRO 0002h 15:8 Reserved 0003h 7:0 BOLMT1 SU.MACAH 0004h Reserved 31:24 0005h 23:16 Reserved 0006h ...
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DDR AME IT 110h RESERVED – Reserved initialize to FF 111h RESERVED – Reserved initialize to FF 112h RESERVED – Reserved initialize to FF 113h RESERVED – Reserved initialize to FF 200h SU.RxFrmCtr RXFRMC31 RXFRMC30 RXFRMC29 ...
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Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, MCLK configuration, and BPCLK configuration. These registers are preserved to provide code compatibility with the multiport devices ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO is turned off 1 = REF_CLKO is disabled and outputs an active low signal. 0 ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default - - Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1) This bit is set the receive clock for Serial Interface ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE) Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: BERT Interrupt Status (BIS) This bit is set the BERT has an enabled interrupt generating event. Register Name: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue read pointer for connection 1. This queue pointer ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: Wrap Type (WT) This bit is used to configure the wrap mode Sequential 1 = Interleave Bits 0- 2: Burst ...
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Register Name: Register Description Register Address: Bit # 7 6 Name SREFT7 SREFT6 Default 0 1 Bits SDRAM Refresh Time Control (SREFT0 – SREFT7) These 8 bits are used to control the SDRAM refresh frequency. The refresh ...
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Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data ...
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BERT Registers Register Name: Register Description: Register Address: Bit # 7 6 Name - PMU Default 0 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU) This bit causes a ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - QRSS Default 0 0 The BERT’s BPCLR, BPCHR, and BSPB registers are used for polynomial-based pattern generation, with formula ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BSP7 BSP6 Default 0 0 Bits BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Register description follows next register. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bits 3 – 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are inserted in the output data ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default - - Bit 3: Performance Monitor Update Status Latched (PMSL) This bit is set when the PMS bit transitions from Bit 2: Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name BEC7 BEC6 Default 0 0 Bits Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits. Register description below. Register Name: Register Description: Register Address: Bit ...
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Bit # 7 6 Name BC15 BC14 Default 0 0 Bits Bit Count (BC[8:15]) Eight bits bit value. Register description below. Register Name: Register Description: Register Address: Bit # 7 6 Name BC23 BC22 ...
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Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to the Serial ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TIFG7 TIFG6 Default 0 0 Bits Transmit Inter-Frame Gapping (TIFG[7:0]) – These eight bits indicate the number of additional flags and bytes of inter-frame fill to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MEIMS TPER6 Default 0 0 Bit 7: Manual Error Insert Mode Select (MEIMS) – When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of errored packets indicated by the TPEN[7:0] bits ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TPC7 TPC6 Default 0 0 Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TBC7 TBC6 Default 0 0 Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Transmit Manual Error Insertion (TMEI) A zero to one transition will insert a single error in the Transmit direction. Register Name: LI.THPMUU ...
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X.86 Registers X.86 Transmit and common Registers are used to control the operation of the X.86 encoder and decoder. Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: X.86 Encoding ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TRSAPIL7 TRSAPIL6 Default 0 0 Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0-7) This is the address field for the X.86 transmitter and expected value for the receiver. ...
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Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMX7 RMX6 Default 1 1 Bits Receive Maximum Packet Size (RMX[7:0]) Eight bits of a sixteen bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPL RAPL Default - - Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is set when a packet with an errored FCS is detected. Bit 6: Receive ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REPIE RAPIE Default 0 0 Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set. ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RPC7 RPC6 Default 0 0 Bits Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RFPC7 RFPC6 Default 0 0 Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RAPC7 RAPC6 Default 0 0 Bits Receive Aborted Packet Count (RAPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RSPC7 RSPC6 Default 0 0 Bits Receive Size Violation Packet Count (RSPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RBC7 RBC6 Default 0 0 Bits Receive Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name REBC7 REBC6 Default 0 0 Bits Receive Aborted Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register ...
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Register Name: LI.RHPMUU Register Description: Serial Interface Receive HDLC PMU Update Register Register Address: 120h Bit # 7 6 Name - - Default 0 0 Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor block performance ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: SAPI Octet not equal to LI.TRX86SAPIH Interrupt Enable (SAPINE01IM) If this bit is set to 1, LI.RX86S.SAPIHNE will generate an interrupt. Bit ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name TQHT7 TQHT6 Default 0 0 Bits 0 – 7: Transmit Queue High Threshold (TQHT[0:7]) The transmit queue high threshold for the connection, in increments of 32 packets of 2048 ...
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Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACRD1 MACRD1 Bits MAC Read Data 1 (MACRD8-15) One of four bytes of data read from the MAC. Valid after a read ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACWD1 MACWD1 5 4 Default 0 0 Bits 0 – 7: MAC Write Data 1 (MACWD8-15) One of four bytes of data to be written to the MAC. Data ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MACAW MACAW Bits 0 – 7: MAC Write Address (MACAW8-15) High byte of the MAC address. Used only for write operations. Register Name: Register Description: ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 0: Queue Loopback Enable (QLP) If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - - Default 0 0 Bit 3: No Carrier Queue Flush Bar (NCFQ) If this bit is set to 1, the queue for data passing from Serial Interface to ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name UR EC Default 0 0 Bit 7: Under Run (UR) When this bit is set to 1, the frame was aborted due to a data under run condition of ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name FL7 FL6 Default 0 0 Bits Frame Length (FL[0:7]) These 8 bits are the low byte of the length (in bytes) of the received frame, with ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name MF - Default 0 0 Bit 7: Missed Frame (MF) This bit is set the packet is not successfully received from the MAC by the packet ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name RMPS7 RMPS6 Default 1 1 Bits 7- 0: Receiver Maximum Frame (RMPS[0:7]) Eight bits of sixteen-bit value. Register description below. Register Name: Register Description: Register Address: Bit # 7 ...
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Note that the receive queue is for data that was received from the Ethernet Interface to be sent to the Serial Interface. Register Name: Register Description: Register Address: Bit # 7 6 Name ...
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Register Name: Register Description: Register Address: Bit # 7 6 Name - UCFR Default 0 0 Bit 6: Uncontrolled Control Frame Reject (UCFR) When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal ...
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MAC Registers The control Registers related to the control of the individual Mac’s are shown in the following table. The DS33Z11 keeps statistics for the packet traffic sent and received. The register address map is shown in the following ...
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Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY) When set to ...
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Register Name: Register Description: Register Address: 0004h: Bit # 31 30 Name Reserved Reserved Default 1 1 0005h: Bit # 23 22 Name Reserved Reserved Default 1 1 0006h: Bit # 15 14 Name PADR47 PADR46 Default 1 1 0007h: ...
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Register Name: Register Description: Register Address: 0014h: Bit # 31 30 Name Reserved Reserved Default 0 0 0015h: Bit # 23 22 Name Reserved Reserved Default 0 0 0016h: Bit # 15 14 Name PHYA4 PHYA3 Default 0 1 0017h: ...
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Register Name: Register Description: Register Address: 0018h: Bit # 31 30 Name Reserved Reserved Default 0 0 0019h: Bit # 23 22 Name Reserved Reserved Default 0 0 001Ah: Bit # 15 14 Name MIID15 MIID14 Default 0 0 001Bh: ...
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Register Name: Register Description: Register Address: 001Ch: Bit # 31 30 Name PT15 PT14 Default 0 0 001Dh: Bit # 23 22 Name PT07 PT06 Default 0 1 001Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 001Fh: ...
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Register Name: Register Description: Register Address: 0100h: Bit # 31 30 Name Reserved Reserved Default 0 0 0101h: Bit # 23 22 Name Reserved Reserved Default 0 0 0102h: Bit # 15 14 Name Reserved Reserved Default 0 0 0103h: ...
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Register Name: Register Description: Register Address: 010Ch: Bit # 31 30 Name Reserved Reserved Default 0 0 010Dh: Bit # 23 22 Name Reserved Reserved Default 0 0 010Eh: Bit # 15 14 Name Reserved Reserved Default 0 0 010Fh: ...
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Register Name: Register Description: Register Address: 0110h: Bit # 31 30 Name Reserved Reserved Default 0 0 0111h: Bit # 23 22 Name Reserved Reserved Default 0 0 0112h: Bit # 15 14 Name Reserved Reserved Default 0 0 0113h: ...
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Register Name: Register Description: Register Address: 0200h: Bit # 31 30 Name RXFRMC3 RXFRMC3 1 0 Default 0 0 0201h: Bit # 23 22 Name RXFRMC2 RXFRMC2 3 2 Default 0 0 0202h: Bit # 15 14 Name RXFRMC1 RXFRMC1 ...
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Register Name: Register Description: Register Address: 0204h: Bit # 31 30 Name RXFRMOK RXFRMOK 31 30 Default 0 0 0205h: Bit # 23 22 Name RXFRMOK RXFRMOK 23 22 Default 0 0 0206h: Bit # 15 14 Name RXFRMOK RXFRMOK ...
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Register Name: Register Description: Register Address: 0300h: Bit # 31 30 Name TXFRMC3 TXFRMC3 1 0 Default 0 0 0301h: Bit # 23 22 Name TXFRMC2 TXFRMC2 3 2 Default 0 0 0302h: Bit # 15 14 Name TXFRMC1 TXFRMC1 ...
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Register Name: Register Description: Register Address: 0308h: Bit # 31 30 Name TXBYTEC3 TXBYTEC3 1 0 Default 0 0 0309h: Bit # 23 22 Name TXBYTEC2 TXBYTEC2 3 2 Default 0 0 030Ah: Bit # 15 14 Name TXBYTEC1 TXBYTEC1 ...
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Register Name: Register Description: Register Address: 030Ch: Bit # 31 30 Name TXBYTEOK TXBYTEOK 31 30 Default 0 0 030Dh: Bit # 23 22 Name TXBYTEOK TXBYTEOK 23 22 Default 0 0 030Eh: Bit # 15 14 Name TXBYTEOK TXBYTEOK ...
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Register Name: Register Description: Register Address: 0334h: Bit # 31 30 Name TXFRMU3 TXFRMU30 1 Default 0 0 0335h: Bit # 23 22 Name TXFRMU2 TXFRMU22 3 Default 0 0 0336h: Bit # 15 14 Name TXFRMU1 TXFRMU14 5 Default ...
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Register Name: Register Description: Register Address: 0338h: Bit # 31 30 Name TXFRMBD TXFRMBD 31 30 Default 0 0 0339h: Bit # 23 22 Name TXFRMBD TXFRMBD 23 22 Default 0 0 033Ah: Bit # 15 14 Name TXFRMBD TXFRMBD ...
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FUNCTIONAL TIMING 10.1 Functional Serial I/O Timing The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an input signal that can be used to enable or block the TSER data. The ...
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The DS33Z11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86 (LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure. TBSYNC is active high on the last bit ...
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Figure 10-5 MII Transmit Functional Timing TX_CLK P R TXD[3:0] TX_EN Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing TX_CLK TXD[3: TX_EN CRS COL Receive Data (RXD[3:0]) is clocked from the external ...
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RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss. Figure 10-9 ...
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Table 10-1 EEPROM Program Memory Map Functional Block Global Registers Arbiter Registers BERT Registers Serial Interface Tx Registers Serial Interface Rx Registers Ethernet Interface Registers MAC Register Write 1 MAC Register Write 2 MAC Register Write 3 MAC Register Write ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to V +5.5V Supply Voltage Range (VDD3.3) with Respect to V +3.6V Supply Voltage Range (VDD1.8) with Respect to V +2.0V Ambient Operating Temperature Range…………………………………………………………………...–40°C to +85°C ...
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PARAMETER Input Leakage Output Leakage (when Hi-Z) Output Voltage (I = -4.0mA) OH Output Voltage (I = +4.0mA) OL Output Voltage (I = -8.0mA) OH Output Voltage (I = +12.0mA) OL Input Voltage Note 1: Typical power is 145mW. Note ...
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Transmit MII Interface PARAMETER SYMBOL TX_CLK Period TX_CLK Low Time TX_CLK High Time TX_CLK to TXD, TX_EN Delay Figure 11-1 Transmit MII Interface TX_CLK TXD[3:0] TX_EN 10 Mbps MIN TYP MAX t1 400 t2 140 260 t3 140 260 ...
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Receive MII Interface PARAMETER SYMBOL RX_CLK Period RX_CLK Low Time RX_CLK High Time RXD, RX_DV to RX_CLK Setup Time RX_CLK to RXD, RX_DV Hold Time Figure 11-2 Receive MII Interface Timing RX_CLK RXD[3:0] RX_DV 10 Mbps MIN TYP MAX ...
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Transmit RMII Interface PARAMETER SYMBOL REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time REF_CLK to TXD, TX_EN Delay Figure 11-3 Transmit RMII Interface REF_CLK TXD[1:0] TX_EN 10 Mbps MIN TYP MAX 50MHz, ±50ppm ...
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Receive RMII Interface PARAMETER SYMBOL REF_CLK Frequency REF_CLK Period REF_CLK Low Time REF_CLK High Time RXD, CRS_DV to REF_CLK Setup Time REF_CLK to RXD, CRS_DV Hold Time Figure 11-4 Receive RMII Interface Timing REF_CLK RXD[1:0] CRS_DV 10 Mbps MIN ...
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MDIO Interface PARAMETER SYMBOL MDC Frequency MDC Period MDC Low Time MDC High Time MDC to MDIO Output Delay MDIO Setup Time MDIO Hold Time Figure 11-5 MDIO Timing MDC MDIO MDC MDIO MIN TYP 1.67 t1 540 600 ...
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Transmit WAN Interface PARAMETER SYMBOL TCLKI Frequency TCLKI Period TCLKI Low Time TCLKI High Time TCLKI to TSER Output Delay TBSYNC Setup Time TBSYNC Hold Time Figure 11-6 Transmit WAN Timing TCLKI TSER TBSYNC MIN TYP MAX 52 t1 ...
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Receive WAN Interface PARAMETER SYMBOL RCLKI Frequency RCLKI Period RCLKI Low Time RCLKI High Time RSER Setup Time RDEN Setup Time RBSYNC Setup Time RDEN Setup Time RBSYNC Setup Time RSER Hold Time RBSYNC Hold Time RDEN Hold Time ...
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SDRAM Timing Table 11-3 SDRAM Interface Timing PARAMETER SDCLKO Period SDCLKO Duty Cycle SDCLKO to SDATA Valid; Write to SDRAM SDCLKO to SDATA Drive On; Write to SDRAM SDCLKO to SDATA Invalid; Write to SDRAM SDCLKO to SDATA Drive ...
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Figure 11-8 SDRAM Interface Timing SDCLKO (output) SDATA (output) SDATA (input) SRAS, SCAS, SWE, SDCS (output) SDA, SBA (output) SDMASK (output t11 t13 157 of 172 t10 t12 t14 ...
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AC Characteristics—Microprocessor Bus Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8 ±5%; T PARAMETER Setup Time for A[12:0] Valid to CS Active Setup Time for CS Active to Either Active Delay Time from Either RD or ...
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Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00) Address Valid ADDR[12:0] DATA[7: Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00) Address Valid ADDR[12:0] DATA[7: ...
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Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01) Address Valid ADDR[12:0] DATA[7: Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01) Address Valid ADDR[12:0] DATA[7: ...
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EEPROM Interface Timing PARAMETER SYMBOL SPICK Period SPICK Low Time SPICK High Time MOSI Setup Delay MISO Hold MISO Setup MISO Hold SPI_CS Hold Figure 11-13 EEPROM Interface Timing – t2 SPI_CS MOSI MISO MIN TYP ...
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JTAG Interface Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8 ±5%; T PARAMETER JTCLK Clock Period JTCLK Clock High: Low Time (Note 1) JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay ...
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JTAG INFORMATION The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 12-2 for a diagram of the state machine operation. Test-Logic-Reset Upon power-up, ...
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Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in ...
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Figure 12-2 TAP Controller State Diagram Test Logic 1 Reset 0 1 Run Test/ 0 Idle 12.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When ...
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Table 12-1 Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE 12.2.1 SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be ...
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JTAG ID Codes Table 12-2 ID Code Structure REVISION DEVICE ID[31:28] DS33Z11 0000 12.4 Test Registers IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been ...
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Figure 12-3 JTAG Functional Timing (INST) Run Test Select DR Capture (STATE) Reset Idle Scan DR JTCLK JTRST JTMS X JTDI JTDO Output Pin IDCODE Update Exit1 Select DR Select IR Capture Shift DR DR Scan Scan ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 13.1 169-Ball CSBGA, 14mm x 14mm (56-G6035-001) ...
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CSBGA, 10mm x 10mm (DS33ZH11 Only) (56-G6008-001) 171 of 172 ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor. DESCRIPTION 172 of 172 © ...