DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 3

• Manufacturer Part Number: DS33ZH11+
• Description: IC MAPPER ETHERNET 100CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33ZH11+

• Applications: Data Transport
• Interface: Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 100-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9
10
11
12
8.16 T
8.17 R
8.18 X.86 E
8.19 C
8.20 H
9.1
9.2
9.3
9.4
9.5
9.6
10.1 F
10.2 MII
10.3 SPI I
11.1 T
11.2 T
11.3 T
11.4 R
11.5 T
11.6 R
11.7 MDIO I
11.8 T
11.9 R
11.10 SDRAM T
11.11 AC C
11.12 EEPROM I
11.13 JTAG I
12.1 JTAG TAP C
12.2 I
8.15.3 Pattern Monitoring...............................................................................................................................52
8.15.4 Pattern Generation..............................................................................................................................52
DEVICE REGISTERS .....................................................................................................................66
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.3.1
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.6.1
9.6.2
FUNCTIONAL TIMING .................................................................................................................142
OPERATING PARAMETERS.......................................................................................................147
JTAG INFORMATION ..................................................................................................................163
12.2.1 SAMPLE:PRELOAD .........................................................................................................................167
12.2.2 BYPASS............................................................................................................................................167
12.2.3 EXTEST ............................................................................................................................................167
12.2.4 CLAMP..............................................................................................................................................167
12.2.5 HIGHZ ...............................................................................................................................................167
R
G
A
BERT R
S
E
NSTRUCTION
RANSMIT
UNCTIONAL
HERMAL
HETA
RANSMIT
RANSMIT
RANSMIT
RBITER
ERIAL
THERNET
ECEIVE
OMMITTED
ARDWARE
EGISTER
ECEIVE
ECEIVE
ECEIVE
LOBAL
AND
Global Register Bit Map ......................................................................................................................67
Arbiter Register Bit Map......................................................................................................................68
BERT Register Bit Map.......................................................................................................................68
Serial Interface Register Bit Map ........................................................................................................69
Ethernet Interface Register Bit Map....................................................................................................71
MAC Register Bit Map ........................................................................................................................72
Arbiter Register Bit Descriptions.........................................................................................................83
Serial Interface Transmit and Common Registers..............................................................................91
Serial Interface Transmit Register Bit Descriptions ............................................................................91
Transmit HDLC Processor Registers .................................................................................................92
X.86 Registers ....................................................................................................................................99
Receive Serial Interface....................................................................................................................101
Ethernet Interface Register Bit Descriptions.....................................................................................114
MAC Registers..................................................................................................................................126
NTERFACE
HARACTERISTICS
-JA
NCODING AND
NTERFACE
NTERFACE
I
NTERFACE
R
RMII I
EGISTERS
R
P
MII I
RMII I
WAN I
C
EGISTER
P
MII I
RMII I
WAN I
B
ACKET
EGISTERS
VS
IMING
I
HARACTERISTICS
NTERFACE
NTERFACE
M
ACKET
IT
I
S
NFORMATION
. A
R
ONTROLLER
NTERFACE
ODE
M
ERIAL
NTERFACES
NTERFACE
EGISTER
NTERFACE
M
IRFLOW
NTERFACE
.........................................................................................................................................156
APS
NTERFACE
NTERFACE
P
ODE AND
........................................................................................................................................62
......................................................................................................................................153
T
.......................................................................................................................................84
P
R
D
ROCESSOR
IMING
.....................................................................................................................................67
ROCESSOR
I/O T
EGISTERS
EFINITIONS
....................................................................................................................................83
D
—M
T
R
ECODING
IMING
.............................................................................................................................148
.............................................................................................................................150
.............................................................................................................................166
EGISTERS
...........................................................................................................................149
...........................................................................................................................162
IMING
S
..........................................................................................................................152
R
ICROPROCESSOR
.........................................................................................................................143
.........................................................................................................................155
EEPROM P
........................................................................................................................151
TATE
ATE
.......................................................................................................................154
......................................................................................................................148
.....................................................................................................................161
.....................................................................................................................54
.....................................................................................................................91
..................................................................................................................142
...................................................................................................................53
...................................................................................................................57
...................................................................................................................74
C
M
ONTROLLER
..............................................................................................................114
ACHINE
ROGRAM
D
B
ESCRIPTION
US
..............................................................................................60
3 of 172
S
T
EQUENCE
IMING
............................................................................158
............................................................................163
......................................................................145