N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 77
N25Q128A11B1240F
Manufacturer Part Number
N25Q128A11B1240F
Description
IC SRL FLASH 128MB NMX 24-BGA
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11B1240F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11B1240F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11B1240F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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Note:
In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program
(DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP),
Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE),
Bulk Erase (BE), Write Status Register (WRSR), Clear Flag Status Register (CLFSR), Write
to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced
Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write
Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That
is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory array are ignored during:
The following continue unaffected, with one exception:
The only exception is the Program/Erase Suspend instruction (PES), that can be used to
pause all the program and the erase cycles except for:
The suspended program or erase cycle can be resumed by the Program/Erase Resume
instruction (PER). During the program/erase cycles, the polling instructions (both on the
Status register and on the Flag Status register) are also accepted to allow the application to
check the end of the internal modify cycles.
These polling instructions don't affect the internal cycles performing.
–
–
–
–
–
–
–
–
–
–
–
Write Status Register cycle
Write Non Volatile Configuration Register
Program cycle
Erase cycle
Internal Write Status Register cycle,
Write Non Volatile Configuration Register,
Program cycle,
Erase cycle
Program OTP (POTP),
Bulk Erase,
Write Non Volatile Configuration Register.
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