N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 19
N25Q128A11B1240F
Manufacturer Part Number
N25Q128A11B1240F
Description
IC SRL FLASH 128MB NMX 24-BGA
Manufacturer
Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
Series
Forté™r
Datasheet
1.N25Q128A11B1241F.pdf
(185 pages)
Specifications of N25Q128A11B1240F
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
128M (16M x 8)
Speed
108MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
1.7 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-TBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
N25Q128A11B1240F
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
N25Q128A11B1240F
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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3
SPI Modes
These devices can be driven by a micro controller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
bus master is in standby mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 5.
Shown here is an example of three devices working in Extended SPI protocol for simplicity
connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one
device drives the serial data output (DQ1) line at a time; the other devices are high
impedance. Resistors R ensures that the N25Q128 is not selected if the bus master leaves
the S line in the high impedance state. As the bus master may enter a state where all
inputs/outputs are in high impedance at the same time (for example, when the bus master is
reset), the clock line (C) must be connected to an external pull-down resistor so that, when
all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled
Low. This ensures that S and C do not become High at the same time, and so that the t
requirement is met. The typical value of R is 100 kΩ, assuming that the time constant R*C
CS3
SPI interface with
(CPOL, CPHA) =
SPI Bus Master
(0, 0) or (1, 1)
CS2 CS1
Bus master and memory devices on the SPI bus
SDO
SDI
SCK
R
R
C
S
DQ1DQ0
SPI memory
device
W
V
CC
HOLD
V
R
SS
C
S
Figure
DQ1 DQ0
SPI memory
device
W
5, is the clock polarity when the
V
HOLD
CC
R
V
SS
C
S
DQ1DQ0
SPI memory
device
W
V
CC
HOLD
AI13725b
19/185
SHCH
V
V
V
SS
CC
SS
p
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