N25Q128A11B1240F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11B1240F Datasheet - Page 134

• Manufacturer Part Number: N25Q128A11B1240F
• Description: IC SRL FLASH 128MB NMX 24-BGA
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: Forté™r

Specifications of N25Q128A11B1240F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: N25Q128A11B1240F

Table 24.
9.3.1
134/185
WRNVCR
RDVCR
WRVCR
RDVECR
WRVECR
DP
RDP
Instruction
Instruction set: QIO-SPI protocol (page 2 of 2)
1)
2)
Multiple I/O Read Identification (MIORDID)
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the QIO-SPI protocol:
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes, see
Identification
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 4 pins DQ0, DQ1, DQ2 and DQ3. After this, the
24-bit device identification, stored in the memory, will be shifted out on again in parallel on
DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out 4 at a time during the falling
edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Multiple I/O Read Identification (MIORDID) instruction sequence and data-out sequence
QIO-SPI.
Write NV Configuration Register
Read Volatile Configuration Register 1000 0101
Write Volatile Configuration Register 1000 0001
Read Volatile Enhanced
Configuration Register
Write Volatile Enhanced
Configuration Register
Deep Power-down
Release from Deep Power-down
The number of Dummy Clock cycles is configurable by the use
SSE is only available in devices with Bottom or Top architecture
Manufacturer identification (1 byte)
Device identification (2 bytes)
Description
(RDID).
1010 1011
1011 0001
0110 0101
1011 1001
0110 0001
Code (BIN)
Instruction
One-byte
B1h
85h
81h
65h
61h
B9h
ABh
Instruction
One-byte
(HEX)
Code
0
0
0
0
0
0
0
Address
bytes
r.
0
0
0
0
0
0
0
Dummy
clock
cycle
9.1.1: Read
2
1 to
1
1 to
1
0
0
bytes
Data
∞
∞