CC-9P-V526UJ-S Digi International, CC-9P-V526UJ-S Datasheet - Page 29

• Manufacturer Part Number: CC-9P-V526UJ-S
• Description: MOD 9P 32MB SDRAM 8MB FLASH
• Manufacturer: Digi International
• Series: -r

Specifications of CC-9P-V526UJ-S

• Module/board Type: Core Module
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Networking

C l o c k g e n e r a t i o n
Clock frequencies
Changing the
CPU speed
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ConnectCore 9P 9215, Wi-9P 9215, and 3G 9P 9215 Hardware Reference
Hardware strapping determines the initial powerup PLL settings. The table below
summarizes the default clock frequencies for the ConnectCore 9P 9215,
ConnectCore Wi-9P 9215, and ConnectCore 3G 9P 9215 modules:
After powerup, software can change the PLL settings by writing to the PLL
configuration register (@ 0xA090_0188)
Important:
stabilize. Applications using this feature need to
lost. See reset behavior in the table below.
Hardware strapping:
"PLL reference clock divider setting:
A[4:0] = 0x1D (0b11101)
NR = 5
"PLL output divider setting:
A[6:5] = 0x3 (0b11)
OD = 0
"PLL bypass setting:
A[7] = 0x1 (0b1)
Normal operation
PLL frequency formula:
PLL Vco = (RefClk / NR+1) * (NF+1)
ClkOut = PLL Vco / (OD+1)
RefClk (Crystal) = 29.4912MHz
NF = 0x3C (reset value - can only be changed by software).
PLL Vco = (29.4912 / 6) * 61 = 299.8272 MHz
ClkOut = 299.8272 MHz
Resulting clock settings:
PIC clock = 299.8272 MHz
CPU clock = 299.8272 MHz / 2 = 149.9136 MHz
AHB clock = 149.9136 MHz / 2 = 74.9568 MHz
When PLL parameters are changed, a reset is provided for the PLL to
be aware the SDRAM contents will be