PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 72

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13.2.36 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
3
4
5
6
7
Bit
1:0
3:2
Function
Target Abort
During Posted
Write
Master Abort
On Posted
Write
Delayed Write
Non-Delivery
Delayed Read –
No Data From
Target
Reserved
Function
S_CLKOUT[0]
disable
Clock 1 disable
Type
RW
RW
RW
RW
RO
Type
RW
RW
Description
Controls bridge’s ability to assert P_SERR# when it receives a target abort when
attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the
command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls bridge’s ability to assert P_SERR# when it receives a master abort when
attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the
command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls bridge’s ability to assert P_SERR# when it is unable to transfer delayed
write data after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the
command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls bridge’s ability to assert P_SERR# when it is unable to transfer any read
data from the target after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit in the
command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Description
S_CLKOUT[0] (slot 0) Enable
00: enable S_CLKOUT[0]
01: enable S_CLKOUT[0]
10: enable S_CLKOUT[0]
11: disable S_CLKOUT[0] and driven LOW
Reset to 00
S_CLKOUT[1] (slot 1) Enable
00: enable S_CLKOUT[1]
01: enable S_CLKOUT[1]
10: enable S_CLKOUT[1]
11: disable S_CLKOUT[1] and driven LOW
Reset to 00
Page 72 of 82
24
attempts.
24
attempts.
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A