PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 30

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.8.3.2 POSTED WRITE TARGET TERMINATION RESPONSE
The bridge makes 2
Table 2-7. Delayed Write Target Termination Response
After the bridge makes 2
the bridge asserts P_SERR# if the SERR# enable bit (bit 8 of command register for the secondary bus)
is set and the delayed-write-non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of
P_SERR# event disable register (offset 64h). The bridge will report system error. See Section 5.4 for a
description of system error conditions.
When the bridge initiates a posted write transaction, the target termination cannot be passed back to the
initiator. Table 2-8 shows the response to each type of target termination that occurs during a posted
write transaction.
Table 2-8. Response to Posted Write Target Termination
Note that when a target retry or target disconnect is returned and posted write data associated with that
transaction remains in the write buffers, the bridge initiates another write transaction to attempt to
deliver the rest of the write data. If there is a target retry, the exact same address will be driven as for
the initial write trans-action attempt. If a target disconnect is received, the address that is driven on a
subsequent write transaction attempt will be updated to reflect the address of the current DWORD. If
the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write
data to the target is performed before a target disconnect is received, the bridge will use the memory
write command to deliver the rest of the write data. It is because an incomplete cache line will be
transferred in the subsequent write transaction attempt.
After the bridge makes 2
associated with that transaction, the bridge asserts P_SERR# if the primary SERR# enable bit is set (bit
8 of command register for secondary bus) and posted-write-non-delivery bit is not set. The posted-
write-non-delivery bit is the bit 2 of P_SERR# event disable register (offset 64h). The bridge will report
system error. See Section 5.4 for a discussion of system error conditions.
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Bridge completes at least one data transfer.
Bridge receives a master abort.
Bridge receives a target abort.
24
(default) or 2
Response
Returning disconnect to initiator with first data transfer only if multiple data phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data phases requested.
Returning target abort to initiator. Set received target abort bit in target interface status register.
Set signaled target abort bit in initiator interface status register.
24
Repsonse
No additional action.
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
24
Repeating write transaction to target.
(default) write transaction attempts and fails to deliver all posted write data
(default) attempts of the same delayed write trans-action on the target bus,
32
(maximum) write attempts resulting in a response of target retry.
Page 30 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
PI7C8140A