PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 26

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
2.7.3 TYPE 1 TO TYPE 1 FORWARDING
The bridge asserts a unique address line based on the device number. These address lines may be used
as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the
Type 1 address bits P_AD[15:11]. presents the mapping that the bridge uses.
Table 2-6. Device Number to IDSEL S_AD Pin Mapping
The bridge can assert up to 16 unique address lines to be used as IDSEL signals for
up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. Because of
electrical loading constraints of the PCI bus, more than 9 IDSEL signals should not be necessary.
However, if device numbers greater than 15 are desired, some external method of generating IDSEL
lines must be used, and no upper address bits are then asserted. The configuration transaction is still
translated and passed from the primary bus to the secondary bus. If no IDSEL pin is asserted to a
secondary device, the transaction ends in a master abort.
The bridge forwards Type 1 to Type 0 configuration read or write transactions as delayed transactions.
Type 1 to Type 0 configuration read or write transactions are limited to a single 32-bit data transfer.
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism when two or
more levels of PCI-to-PCI bridges are used.
When the bridge detects a Type 1 configuration transaction intended for a PCI bus downstream from
the secondary bus, the bridge forwards the transaction unchanged to the secondary bus. Ultimately, this
transaction is translated to a Type 0 configuration command or to a special cycle transaction by a
downstream PCI-to-PCI bridge. Downstream Type 1 to Type 1 forwarding occurs when the following
conditions are met during the address phase:
Device Number
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
10h – 1Eh
1Fh
Leaves unchanged the function number and register number fields.
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus
number register and the upper limit (inclusive) in the subordinate bus number register.
P_AD[15:11]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000 – 11110
11111
Secondary IDSEL S_AD[31:16]
0000 0000 0000 0001
0000 0000 0000 0010
0000 0000 0000 0100
0000 0000 0000 1000
0000 0000 0001 0000
0000 0000 0010 0000
0000 0000 0100 0000
0000 0000 1000 0000
0000 0001 0000 0000
0000 0010 0000 0000
0000 0100 0000 0000
0000 1000 0000 0000
0001 0000 0000 0000
0010 0000 0000 0000
0100 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
Generate special cycle (P_AD[7:2] > 00h)
0000 0000 0000 0000 (P_AD[7:2] = 00h)
Page 26 of 82
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
S_AD
16
17
18
19
20
21
22
23
24
25
26
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28
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PI7C8140A