PI7C8140AMAE Pericom Semiconductor, PI7C8140AMAE Datasheet - Page 59

• Manufacturer Part Number: PI7C8140AMAE
• Description: IC PCI-PCI BRIDGE 2PORT 128-QFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8140AMAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 128-QFP
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 230 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

07-0067
13
13.1 REGISTER TYPES
13.2 CONFIGURATION REGISTER
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte DWORD to define various attributes of PI7C8140A as shown
below.
REGISTER TYPE
RO
RW
RWC
RWR
RWS
Secondary Latency
Arbiter Preemption
Secondary Bus
Prefetchable Memory Limit Address
Secondary Master Timeout Counter
CLKRUN
Reserved
Reserved
Reserved
Power Management Capabilities
Control
31 – 24
I/O Limit Address Upper 16-bit
Timer
Memory Limit Address
Secondary Status
Arbiter Control
Bridge Control
Primary Status
Subsystem ID
Device ID
Reserved
Reserved
Reserved
Prefetchable Memory Limit Address Upper 32-bit
Prefetchable Memory Base Address Upper 32-bit
P_SERR# Status
Subordinate Bus
Header Type
Class Code
Reserved
Reserved
Reserved
Number
HSCSR
23 – 16
DEFINITION
Read Only
Read / Write
Read / Write 1 to Clear
Read / Write 1 to Reset (for about 20 clocks)
Read / Write 1 to Set
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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I/O Limit Address
Next Item Pointer
Next Item Pointer
Primary Latency
Secondary Bus
Interrupt Pin
Prefetchable Memory Base Address
Reserved
Reserved
Primary Master Timeout Counter
Number
I/O Base Address Upper 16-bit
15 – 8
Timer
Diagnostic / Chip Control
Secondary Clock Control
Power Management Data
Extended Chip Control
Memory Base Address
Subsystem Vendor ID
Port Option
Vendor ID
Command
Capability Pointer
I/O Base Address
Hot Swap Switch
Cache Line Size
P_SERR# Event
Interrupt Line
Capability ID
Capability ID
Primary Bus
Revision ID
Number
Disable
7 – 0
2-PORT PCI-TO-PCI BRIDGE
March 20, 2007 – Revision 1.01
DWORD ADDRESS
78h – 7Ch
98h – BFh
10h – 14h
50h – 60h
0Ch
1Ch
2Ch
3Ch
4Ch
6Ch
8Ch
00h
04h
08h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
64h
68h
70h
74h
80h
84h
88h
90h
94h
PI7C8140A