IDT77V011L155DA IDT, Integrated Device Technology Inc, IDT77V011L155DA Datasheet

IDT77V011L155DA

Manufacturer Part Number

IDT77V011L155DA

Description

INTERFACE DPI-UTOPIA 144-TQFP

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT77V011L155DA.pdf (43 pages)

Specifications of IDT77V011L155DA

Interface

DPI, UTOPIA

Voltage - Supply

3 V ~ 3.6 V

Package / Case

144-TQFP, 144-VQFP

Mounting Type

Surface Mount

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Applications

Other names

77V011L155DA

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) ) ) ) H H H H D D D D W X W X W X W X U U U U H V H V H V H V

' H V F U L S W L R Q

Data Path Interface (DPI) and an 8 or 16-bit UTOPIA Level 2 interface.

DPI offers a reduced device pin count and gives the IDT77V400

Switching Memory a high degree of port configuration flexibility.

% O R

% O R F F F F N ' L

2001 Integrated Device Technology, Inc.

The IDT77V011provides the interface translation between a 4 or 8-bit

‹

Single chip interface between multiple UTOPIA PHYs and a

single Data Path Interface (DPI).

Ideal for xDSL DSLAM and 25Mbps switching applications.

Supports ATM Forum UTOPIA Level 2 interface in both 8-bit

and 16-bit modes.

Supports UTOPIA Level 2 Cell Level Handshake.

Supports up to 31 PHYs on the UTOPIA Level 2 interface.

Supports either 4-bit or 8-bit DPI interface.

Supports cell sizes from 52 to 56 bytes on the DPI interface.

Supports DPI operation up to 50MHz.

Either Utility Bus or Parallel Manager Management interface

for configuring and reading status of PHY registers.

In-Stream™ (In-band) programming for configuration of

device and management interface communications.

TAG Routing for flexibility in routing cells.

Single +3.3V ± 0.3V power supply required.

Inputs are +5.0V tolerant.

N ' L

N ' L D J U

D J U

D J U D D D D P P P P

ADSL

PHY

UTOPIA 2 8/16-bit

Figure 1 Typical IDT77011 ADSL DSLAM Application with the IDTV400 Switching Memory

Data Path Interface (DPI) to

Utopia Level 2

Translation Device

ADSL

Management Bus

PHY

ADSL

PHY

1 of 43

interface, the IDT77V011 offers the opportunity to connect up to 31 PHY

ports to a single 155Mbps port of the IDT77V400 Switching Memory.

Routing, with each direction being individually programmed. In the

receive direction up to four bytes can be added to the cell. In the

transmit direction up to four bytes can be removed from the cell. This

makes the IDT77V011, when combined with the IDT77V400, an ideal

component for DSLAM and 25Mbps applications where the user would

like to implement OC-3 bandwidth of a single IDT77V400 port to a

number of lower bandwidth ports.

ration options. The cells are received on the DPI transmit interface, iden-

tified and sent to the internal cell interpreter for decoding and execution.

In-Stream™ programming cells are transmitted based on a round-robin

scheduler, which provides equal priority for each of the subports and the

cell generator. This methodology is also used to communicate and

configure the PHYs that are connected to the IDT77V011.

ization and Discovery/Identify cells, and a Management interface to

access the PHY devices.

By providing a smooth translation to the UTOPIA Level 2 multi-PHY

The IDT77V011 can also provide both transmit and receive TAG

The 77V011 utilizes In-Stream™ programming for its device configu-

Other features include an EEPROM that holds information for initial-

IDT77V011

DPI 4/8-bit

IDT77V400

Switching

Memory

5348drw01

March 15, 2001

IDT77V011

DSC 4308/8

Related parts for IDT77V011L155DA

IDT77V011L155DA Summary of contents

Page 1

Single chip interface between multiple UTOPIA PHYs and ...

Page 4

IDT77V011 RxDATA [10] 103 I RxDATA [11] 104 I RxDATA [12] 105 I RxDATA [13] 106 I RxDATA [14] 107 I RxDATA [15] 110 I RSOC 111 I RCLAV 112 I RENB 121 O RxADDR [0] 120 O RxADDR [1] ...

Page 5

IDT77V011 TxDATA [11 TxDATA [12] 143 O TxDATA [13] 142 O TxDATA [14] 141 O TxDATA [15] 140 O TSOC 134 O TCLAV 126 I TENB 138 O TxADDR[0] 129 O I TxADDR[1] 130 O I TxADDR[2] 131 ...

Page 6

IDT77V011 MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[ MBUS[10 MBUS[11 ...

Page 7

IDT77V011 MDATA[3] 84 I/O MDATA[4] 85 I/O MDATA[5] 86 I/O MDATA[6] 87 I/O MDATA[7] 88 I/O MGMT[ MGMT[ MGMT[ MGMT[ MGMT[ PHYRST 74 O PHYINT 71 I SYSRST ...

IDT77V011 TxREF is a 8KHz reference clock output generated from REFCLK. REFCLK is a 8KHz reference clock input used to generate the TxREF clock signal. TxLED indicates if there is activity on the transmit UTOPIA 2 bus. This signal asserts ...

Page 12

IDT77V011 TCLK (output) TxADDR[4:0] 1B (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] (output) TCLK (output) TxADDR[4:0] 04 (output) TCLAV (input) TENB (output) TSOC (output) TxDATA[7:0] 47 (output) Configuration 1 8001 0 Configuration 2 8002 [1:0] [6:2] Configuration 3 8003 ...

Page 13

IDT77V011 ' ...

Page 14

IDT77V011 DRxCLK (input/ output) DRxFRM (output) DRxDATA[3:0] 104 105 (output) Figure 8 Nibble Mode Back-to-Back Cell Transfer on Receive DPI Bus DTxCLK (output) DTxFRM (input) DTxDATA[3:0] (input) DTxCLK (output) DTxFRM (input) DTxDATA[3:0] 104 105 (input) Figure 10 Nibble Mode Back-to-Back ...

Page 15

IDT77V011 & ...

Page 16

IDT77V011 Pin Controls 801A (I) SYSCLK t t PALE (O) ALE PHYCS (O) (O) RD ...

Page 17

IDT77V011 ...

Page 18

IDT77V011 ...

Page 19

IDT77V011 (O) ADDR[11:0] SEL (O) (I/O) DATA[7:0] (O) WR/RW (O) RD/DS (I) RDY/DTACK (O) RD/DS (O) WR/RW (I) RDY/DTACK BMODE — MBUS[0] Tx TAG Size[0] MBUS[1] Tx TAG Size[1] MBUS[2] Tx TAG Size[2] MBUS[3] TxLOC MBUS[4] TxHEC MBUS[5] Rx TAG ...

Page 20

IDT77V011 MGMT[5] — PHYRST — PHYINT — MGMT[1] CS[0] MBUS[11:0] CS[12:1] MGMT[2] RD MGMT[3] WR MGMT[5] ALE MDATA[7:0] ADDR/DATA[7:0] PHYINT PHYINT PHYRST PHYRST BMODE BMODE MBUS[11:0] ADDR[11:0] MDATA[7:0] DATA[7:0] MGMT[1] SEL MGMT[2] RD/DS MGMT[3] WR/RW MGMT[4] RDY/DTACK PHYRST PHYRST PHYINT ...

Page 21

IDT77V011 ( ( ...

Page 22

IDT77V011 User Defined Reserved Discovery/Identify cell data Reserved In-Stream™ Subport In-Stream™ Cell Header Figure 16 EEPROM Memory Map 0xFFFFFF Reserved 0x008025 0x008024 77V011 Registers 0x008000 0x007FFF Reserved 0x000F00 0x000EFF PHY #30 Registers 0x000E00 0x000DFF PHY #29 Registers 0x000D00 0x000CFF PHY ...

Page 23

IDT77V011 & & ...

Page 24

IDT77V011 In-Stream™ Subport bits[4:0] of DPI Tx Subport Configuration Register Cell Interpreter Register Content Max Subports 0x1E Subport Width 0x5 Replace Subport 1 Bit Location 0x5 Byte Location 0x2 New Subport 0x1F x = Any valid subport address Byte 0 ...

Page 25

IDT77V011 ...

Page 26

IDT77V011 Configuration 2 8002 [6:2] Max Subports Subport 8013 [4:0] In-Stream™ Configuration 1 Subport [7:5] Tx Subport Width 0x0 - 0x7 Modify Tx 8014 [4:0] New Subport Subport 5 Replace Subport 0x0 - 0x7 Tx Subport Position 8015 [2:0] Tx ...

Page 27

IDT77V011 Configuration 1 8001 2 Rx Move PT/CLP Rx TAG 8005 [2:0] Rx Tag Size [2: Remove HEC 4 Rx TAG Location TAG byte 3 8016 [7:0] TAG [31:24] TAG byte 2 8017 [7:0] TAG [23:16] TAG byte ...

Page 28

IDT77V011 , Œ Œ Œ Œ ...

Page 29

IDT77V011 In-Stream™ Cell 800F [7:0] Header Byte 0 In-Stream™ Cell 8010 [7:0] Header Byte 1 In-Stream™ Cell 8011 [7:0] Header Byte 2 In-Stream™ Cell 8012 [7:0] Header Byte 3 Discover/ Identify 2 Reset 3 Read Registers 5 Write Registers 6 ...

Page 30

IDT77V011 UNI Cell Header (five byte field) Bit GFC VPI VCI VCI HEC Figure 21 Valid Header Formats for In-Stream Command Cell Transaction ID (two byte field) Bit Copied from ...

Page 31

IDT77V011 Device ID (seven byte field) Bit Not Used Not Used Not Used Not Used Not Used Not Used Figure 24 Valid Device ID Field Format for In-Stream ...

Page 32

IDT77V011 & & ...

Page 33

IDT77V011 UTOPIA Rx Cell 801B [7:0] Counter byte 3 UTOPIA Rx Cell 801C [7:0] Counter byte 2 UTOPIA Rx Cell 801D [7:0] Counter byte 1 UTOPIA Rx Cell 801E [7:0] Counter byte 0 UTOPIA Tx Cell 801F [7:0] Counter byte ...

Page 34

IDT77V011 t DPI DTxCLK/DRxCLK Cycle Time DCYC t DPI DTxCLK/DRxCLK High Time DCH t DPI DTxCLK/DRxCLK Low Time DCL t DTxFRM, DTxDATA to DTCLK Setup Time DTS t DTxFRM, DTxDATA to DTCLK Hold Time DTH t DRxCLK to DRxDATA(0-3), DRxFRM ...

Page 35

IDT77V011 t ADDR to RD/DS Falling Edge Setup Time ADRS t ADDR to RD/DS Rising Edge Hold Time ADRH t SEL to RD/DS Falling Edge Setup Time SELRS t SEL to RD/DS Rising Edge Hold Time SELRH t DATA Invalid/Tri-state ...

Page 36

IDT77V011 SYSCLK DRxCLK SYSCLK DTxCLK TCLK TxDATA(0-7), TENB, TSOC TCLAV RCLK RxDATA(0-7), RSOC, RCLAV DTxCLK DTxFRM, DTxDATA(0-3) tPDRxCLK Figure 30 System Clock to DPI Receive Clock Propagation Delay tPDTxCLK Figure 31 System Clock to DPI Transmit ...

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