W83977G-A Nuvoton Technology Corporation of America, W83977G-A Datasheet - Page 53

• Manufacturer Part Number: W83977G-A
• Description: IC I/O CONTROLLER 128-PQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83977G-A

• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.6
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
TABLE 6-4 INTERRUPT CONTROL FUNCTION
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
Bit
3
0
0
0
1
0
0
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
out interrupt is pending.
this bit will be set to a logical 0.
Bit
2
0
1
1
1
0
0
Interrupt Status Register (ISR) (Read only)
ISR
Bit
1
0
1
0
0
1
0
7
Bit
0
1
0
0
0
0
0
6
Interrupt
priority
First
Second
Second
Third
Fourth
5
0
-
4
0
Interrupt
Type
UART
Receive
Status
RBR Data
Ready
FIFO Data
Timeout
TBR Empty
Handshake
status
3
-
-45 -
INTERRUPT SET AND FUNCTION
2
Interrupt Source
No Interrupt pending
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active
level reached
Data present in RX FIFO
for 4 characters period of
time since last access of
RX FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
1
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
2. PBER =1
4. TDCD = 1
2. TDSR = 1
Publication Release Date: May 2006
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until
FIFO
active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority
is third)
Read HSR
data under
Revision 0.60
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