W83977G-A Nuvoton Technology Corporation of America, W83977G-A Datasheet - Page 41
W83977G-A
Manufacturer Part Number
W83977G-A
Description
IC I/O CONTROLLER 128-PQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet
1.W83977G-A.pdf
(182 pages)
Specifications of W83977G-A
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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5.2.5
The Main Status Register is used to control the flow of data between the microprocessor and the
controller. The bit definitions for this register are as follows:
5.2.6
The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of
the FDC is programmed by the CC REGISTER for PC-AT and PS/2 Model 30 and PS/2 mode, and
not by the DR REGISTER. The real data rate is determined by the most recent write to either of the
DR REGISTER or CC REGISTER.
S/W RESET (Bit 7):
This bit is the software reset bit.
POWER-DOWN (Bit 6):
0
1
PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2):
These three bits select the value of write precompensation. The following tables show the
precompensation values for the combination of these bits.
7
W83977F-A/ W83977G-A/ W83977AF-A/ W83977AG-A
FDC in normal mode
FDC in power-down mode
6
5
Main Status Register (MS Register) (Read base address + 4)
Data Rate Register (DR Register) (Write base address + 4)
4
3
2
1
7
0
FDD 2 Busy, (D2B = 1), FDD number 2 is in the SEEK mode.
FDD 0 Busy, (D0B = 1), FDD number 0 is in the SEEK mode.
FDD 1 Busy, (D1B = 1), FDD number 1 is in the SEEK mode.
FDD 3 Busy, (D3B = 1), FDD number 3 is in the SEEK mode.
FDC Busy, (CB). A read or write command is in the process when CB = HIGH.
Non-DMA mode, the FDC is in the non-DMA mode, this bit is set only during the
execution phase in non-DMA mode.
Transition to LOW state indicates execution phase has ended.
DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor.
Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor.
If DIO = LOW then transfer is from processor to Data Register.
6
5
0
4
3
-33 -
2
1
0
DRATE0
DRATE1
PRECOMP0
PRECOMP1
PRECOMP2
POWER DOWN
S/W RESET
Publication Release Date: May 2006
Revision 0.60
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