PCA9542APW/DG,118 NXP Semiconductors, PCA9542APW/DG,118 Datasheet - Page 7

• Manufacturer Part Number: PCA9542APW/DG,118
• Description: IC I2C MUX 2-CH 14-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9542APW/DG,118

• Package / Case: 14-TSSOP
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: I2C Bus
• High Level Output Current: 10 uA
• Low Level Output Current: 3 mA
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Input Signal Type: SCL / SDA
• Interface Type: I2C Bus
• Maximum Power Dissipation: 400 mW
• Mounting Style: SMD/SMT
• Output Type: SCx / SDx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935286937118; PCA9542APW/DG-T; PCA9542APW/DG-T

NXP Semiconductors
7. Characteristics of the I
PCA9542A_4
Product data sheet
7.1 Bit transfer
7.2 START and STOP conditions
7.3 System configuration
The I
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see
Fig 7.
Fig 8.
2
C-bus is for 2-way, 2-line communication between different ICs or modules. The two
SDA
SCL
Bit transfer
Definition of START and STOP conditions
START condition
2
SDA
SCL
Figure
C-bus
S
Rev. 04 — 15 June 2009
8).
Figure
data valid
data line
stable;
2-channel I
9).
Figure
allowed
change
of data
7).
2
C-bus multiplexer and interrupt logic
STOP condition
PCA9542A
mba607
P
© NXP B.V. 2009. All rights reserved.
mba608
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