PCA9542APW/DG,118 NXP Semiconductors, PCA9542APW/DG,118 Datasheet - Page 5

• Manufacturer Part Number: PCA9542APW/DG,118
• Description: IC I2C MUX 2-CH 14-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9542APW/DG,118

• Package / Case: 14-TSSOP
• Applications: 2-Channel I²C Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Logic Family: I2C Bus
• High Level Output Current: 10 uA
• Low Level Output Current: 3 mA
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Input Signal Type: SCL / SDA
• Interface Type: I2C Bus
• Maximum Power Dissipation: 400 mW
• Mounting Style: SMD/SMT
• Output Type: SCx / SDx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935286937118; PCA9542APW/DG-T; PCA9542APW/DG-T

NXP Semiconductors
PCA9542A_4
Product data sheet
6.3 Interrupt handling
6.4 Power-on reset
Table 4.
The PCA9542A provides 2 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9542A and the interrupt output will be driven LOW. The channel need not be active
for detection of the interrupt. A bit is also set in the control byte.
Bits 5:4 of the control byte correspond to channel 1, channel 0 of the PCA9542A,
respectively. Therefore, if an interrupt is generated by any device connected to channel 1,
the state of the interrupt inputs is loaded into the control register when a read is
accomplished. Likewise, an interrupt on any device connected to channel 0 would cause
bit 4 of the control register to be set on the read. The master can then address the
PCA9542A and read the contents of the control byte to determine which channel contains
the device generating the interrupt. The master can then reconfigure the PCA9542A to
select this channel, and locate the device generating the interrupt and clear it.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
The interrupt inputs may be used as general purpose inputs if the interrupt function is not
required.
If unused, interrupt input(s) must be connected to V
Table 5.
Remark: The two interrupts can be active at the same time.
When power is applied to V
a reset condition until V
and the PCA9542A registers and I
states (all zeroes), causing all the channels to be deselected. Thereafter, V
lowered below 0.2 V to reset the device.
D7
X
X
X
X
0
D7
0
0
D6
X
X
X
X
0
D6
0
0
Control register: Write—channel selection; Read—channel status
Control register read — interrupt
INT1
X
X
X
X
0
INT1
X
0
1
Rev. 04 — 15 June 2009
INT0
X
X
X
X
0
DD
INT0
X
0
1
has reached V
DD
, an internal Power-On Reset (POR) holds the PCA9542A in
D3
X
X
X
X
0
D3
X
X
2
C-bus state machine are initialized to their default
2-channel I
B2
0
1
1
1
0
B2
POR
X
X
. At this point, the reset condition is released
B1
X
0
0
1
0
B1
X
X
2
C-bus multiplexer and interrupt logic
DD
B0
X
0
1
X
0
through a pull-up resistor.
B0
X
X
Command
no channel selected
channel 0 enabled
channel 1 enabled
no channel selected
no channel selected;
power-up default state
Command
no interrupt on channel 0
interrupt on channel 0
no interrupt on channel 1
interrupt on channel 1
PCA9542A
© NXP B.V. 2009. All rights reserved.
DD
must be
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