LNBS21PD-TR STMicroelectronics, LNBS21PD-TR Datasheet - Page 8

• Manufacturer Part Number: LNBS21PD-TR
• Description: IC LNB SUPPLY & CNTRL 20-PWRSOIC
• Manufacturer: STMicroelectronics

Specifications of LNBS21PD-TR

• Applications: Power Supplies, Converters, Controllers
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 8 V ~ 15 V
• Package / Case: PowerSO-20 Exposed Bottom Pad
• Mounting Type: Surface Mount
• Output Voltage: 22 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5369-2; LNBS21PD-TR

LNBS21
Values are typical unless otherwise specified
POWER-ON I
The I
automatically reset at power-on. As long as the
V
threshold (6.7V typ.), the interface will not respond
to any I
(SR) is initialized to all zeroes, thus keeping the
power blocks disabled. Once the V
7.3V, the I
SR can be configured by the main µP. This is due
to About 500mV of hysteresis provided in the UVL
threshold to avoid false retriggering of the
Power-On reset circuit.
DiSEqC
The LNBS21 helps the system designer to
implement the bi-directional (2.x) DiSEqC protocol
by
demodulation of the 22KHz carrier. The PWK data
are exchanged between the LNBS21 and the
main µP using logic levels that are compatible with
both 3.3 and 5V microcontrollers. This data
exchange is made through two dedicated pins,
DSQIN and DSQOUT, in order to maintain the
timing relationships between the PWK data and
the PWK modulation as accurate as possible.
These two pins should be directly connected to
two I/O pins of the µP, thus leaving to the resident
firmware the task of encoding and decoding the
Table 5: Electrical Characteristics For LNBS Series (T
PCL=0, DSQIN=0, V
for I
8/21
Symbol
PCL
CC
These bits are read exactly the same as
they were left after last write operation
V
V
V
V
I
LT1
2
IN
IN
O
O
C access to the system register)
allowing
stays be-low the UnderVoltage Lockout
2
ISEL
C interface built in the LNBS21 is
TM
2
Supply Voltage
LT1 Input Voltage
Supply Current
Output Voltage
Output Voltage
C command and the System Register
2
C interface becomes operative and the
IMPLEMENTATION
2
TEN
C INTERFACE RESET
an
Parameter
LLC VSEL
IN
easy
=12V, I
OUT
PWK
=50mA, unless otherwise specified. See software description section
EN
CC
I
I
I
I
O
O
O
O
= 750 mA TEN=VSEL=LLC=1
= 0mA TEN=VSEL=LLC=1
= 750 mA VSEL=1
= 750 mA VSEL=0
rises above
modulation/
OTF
0
1
OLF
Test Conditions
0
1
T
T
I
I
OUT
OUT
J
J
<140°C, normal operation
>150°C, power block disabled, Loothrough switch open
PWK data in accordance to the DiSEqC protocol.
Full compliance of the system to the specification
is thus not implied by the bare use of the LNBS21.
The system designer should also take in
consideration the bus hardware requirements,
that include the source impedance of the Master
Transmitter measured at 22KHz. To limit the
attenuation at carrier frequency, this impedance
has to be 15ohm at 22KHz, dropping to zero ohm
at DC to allow the power flow towards the
peripherals. This can be simply accomplished by
the LR termination put on the OUT pin of the
LNBS, as shown in the Typical Application Circuit
on page 5.
Unidirectional (1.x) DiSEqC and non-DiSEqC
systems normally don't need this termination, and
the OUT pin can be directly connected to the LNB
supply port of the Tuner. There is also no need of
Tone Decoding, thus, it is recommended to
connect the DETIN and DSQOUT pins to ground
to avoid EMI.
ADDRESS PIN
Connecting this pin to GND the Chip I
address is 0001000, but, it is possible to choice
among 4 different addresses simply setting this
pin at 4 fixed voltage levels (see table on page
10).
<I
>I
J
OMAX
OMAX
= 0 to 85°C, EN=1, LLC=0, TEN=0, ISEL=0,
, normal operation
, overload protection triggered
EN=1
EN=0
LLC=0
LLC=1
LLC=0
LLC=1
Function
Min.
17.3
12.5
8
Typ.
2.5
20
18
19
13
14
Max.
18.7
13.5
15
20
40
5
2
C interface
Unit
mA
mA
V
V
V
V
V
V