FIN1102MTC Fairchild Semiconductor, FIN1102MTC Datasheet - Page 3

• Manufacturer Part Number: FIN1102MTC
• Description: IC REPEATER 2 PORT LVDS 14TSSOP
• Manufacturer: Fairchild Semiconductor
• Type: Repeaterr

Specifications of FIN1102MTC

• Tx/rx Type: LVDS
• Delay Time: 1.75ns
• Capacitance - Input: 2.5pF
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 23mA
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
PLHD
PHLD
TLHD
THLD
SK(P)
SK(LH)
SK(HL)
SK(PP)
MAX
PZHD
PZLD
PHZD
PLZD
DJ
RJ
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at T
Note 4: t
tion.
Note 5: t
direction (either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: Passing criteria for maximum frequency is the output V
Note 7: Output loading is transmission line environment only; C
FIGURE 1. Differential Receiver Voltage Definitions and
Symbol
,
Propagation and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
SK(LH)
SK(PP)
Differential Output Propagation Delay
LOW-to-HIGH
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%) |V
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
Differential Output Disable Time
from LOW to Z
LVDS Data Jitter,
Deterministic
LVDS Clock Jitter,
Random (RMS)
, t
is the magnitude of the difference in differential propagation delay times between identical channels of two devices switching in the same
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
PLH
Parameter
- t
A
PHL
25 C and with V
|
CC
3.3V, V
R
V
Duty Cycle
See Figure 3 and Figure 4
R
See Figure 5 and Figure 6
|V
V
|V
V
L
IC
L
IC
IC
OD
ID
ID
ID
L
is
|
|
|
ID
100 , C
100 , C
|V
1.2V at 800 Mbps
1.2V at 400 MHz
200 mV and the duty cycle is 45% to 55% with all channels switching.
200 mV to 450 mV,
300 mV, PRBS
300 mV,
1 pF of stray test fixture capacitance.
ID
300 mV, V
|/2 to V
Test Conditions
50%,
L
L
3
CC
5 pF,
5 pF,
IC
Note A: All LVDS input pulses have frequency
Note B: C
1.2V, unless otherwise specified.
(|V
FIGURE 3. Differential Driver Propagation Delay
t
2
F
ID
23
|/2),
L
- 1,
includes all probe and test fixture capacitances
0.5 ns
and Transition Time Test Circuit
0.29
0.75
0.75
0.29
Min
400
(Note 3)
0.02
0.02
0.02
Typ
800
1.1
1.1
0.4
0.4
2.3
2.5
1.6
1.9
2.1
85
10 MHz, t
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Max
1.75
1.75
0.58
0.58
0.15
R
135
0.2
0.5
3.5
5
5
5
5
or
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps