DS1877T+T&R Maxim Integrated Products, DS1877T+T&R Datasheet - Page 27

• Manufacturer Part Number: DS1877T+T&R
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+TRL

<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.
*The final result must be XORed with BB40h before writing to this register.
<C> or <_/C> = Common, <D> or <_/D> = Different, <M> or <_/M> = Mixture of common and different.
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h−C1h).
These registers also allow for custom permissions.
D0–FF
80–C7
C8–F7
(HEX)
(HEX)
F8–FF
ACCESS
Read
Access
Write
Access
ROW
ROW
A0
A8
B0
B8
C0
C8
80
88
90
98
CODE
<8/C>
<4/C>
<8/D>
<8/C>
<9/C>
<0/C>
<8/C>
<8/C>
<8/C>
<8/C>
<8/C>
ROW NAME
ROW NAME
<8/D>
PWD ENABLE
separately
DAC VALUES
DAC OFFSET
THRESHOLD
PWD VALUE
EMPTY
EMPTY
See each
CONFIG 0
CONFIG 1
bit/byte
OFFSET 0
OFFSET 1
SCALE 0
SCALE 1
<0/_>
LUT4
LOS RANGING
<1/_>
DAC OFFSET
PW2
<8/C>
All
BYTE 0/8
BYTE 0/8
DAC LUT
PW_ENA
INTERNAL TEMP OFFSET*
CNFGA
EMPTY
EMPTY
RSSI2 COARSE OFFSET
RSSI2 COARSE SCALE
LUT
MODE
SFP Controller for Dual Rx Interface
DAC2 VALUE
RESERVED
PW1 MSW
WORD 0
WORD 0
<2/_>
2
N/A
All
DAC OFFSET
<4/C>
RESERVED
BYTE 1/9
BYTE 1/9
DAC LUT
PW_ENB
CNFGB
EMPTY
EMPTY
LUT
TINDEX
hardware
DS1877
All and
<3/_>
All
DAC OFFSET
RESERVED
RESERVED
BYTE 2/A
BYTE 2/A
DAC LUT
CNFGC
HLOS2
EMPTY
EMPTY
PW2 +
<4/_>
mode
LUT
PW2
RSSI2 FINE OFFSET
TABLE 04h (DAC LUT)
RSSI2 FINE SCALE
bit
TABLE 02h (PW2)
V CC OFFSET
V CC SCALE
RESERVED
PW1 LSW
WORD 1
WORD 1
DEVICE ADDRESS
<5/_>
DAC OFFSET
RESERVED
RESERVED
All
All
BYTE 3/B
BYTE 3/B
DAC LUT
EMPTY
EMPTY
LLOS2
LUT
<6/_>
N/A
All
LOS RANGING
DAC OFFSET
RESERVED
RESERVED
RESERVED
BYTE 4/C
BYTE 4/C
DAC LUT
EMPTY
EMPTY
RSSI1 COARSE OFFSET
RSSI1 COARSE SCALE
LUT
XOVER2 COARSE
XOVER1 COARSE
<7/_>
PW1
PW1
DAC1 VALUE
PW2 MSW
WORD 2
WORD 2
1
DAC OFFSET
FORCE RSSI
RESERVED
RESERVED
RESERVED
BYTE 5/D
BYTE 5/D
DAC LUT
<8/_>
PW2
PW2
EMPTY
EMPTY
LUT
Table 04h Register Map
Table 02h Register Map
<9/_>
PW2
N/A
<10>
DAC OFFSET
POLARITY
BYTE 6/E
BYTE 6/E
DAC LUT
RSHIFT 2
HLOS1
EMPTY
EMPTY
DEVICE ID
LUT
RSSI1 FINE OFFSET
RSSI1 FINE SCALE
XOVER2 FINE
XOVER1 FINE
<10/_>
RESERVED
PW2
PW2 LSW
WORD 3
WORD 3
N/A
<10>
DAC OFFSET
TBLSELPON
BYTE 7/F
BYTE 7/F
DAC LUT
RSHIFT 1
DEVICE VER
EMPTY
EMPTY
LLOS1
<11/_>
LUT
PW1
All
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