DS1877T+T&R Maxim Integrated Products, DS1877T+T&R Datasheet - Page 20

• Manufacturer Part Number: DS1877T+T&R
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+TRL

SFP Controller for Dual Rx Interface
CNFGA register (Table 02h, Register 88h). External pul-
lup resistors must be provided on OUTX and RSELOUT
to realize high logic levels.
FAULT can be triggered by all alarms, warnings, and
QTs. The six ADC alarms, warnings, and LOS QTs
require enabling (Table 01h/05h, Registers F8h and
FCh). Latching of the alarms is controlled by the CNFGB
and CNFGC registers (Table 02h, Registers 89h−8Ah).
The device has an ID hardcoded in its die. Two registers
(Table 02h, Registers 86h−87h) are assigned for this
feature. Register 86h reads 77h to identify the part as the
DS1877; Register 87h reads the present device version.
The following terminology is commonly used to describe
I
Figure 12. I
20
2
C data transfers.
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
STOP
2
t
BUF
C Timing
START
t
HD:STA
IL(MAX)
I
t
LOW
2
AND V
C Communication
IH(MIN)
t
R
.
Die Identification
t
HD:DAT
I
2
C Definitions
FAULT Output
t
HIGH
t
F
t
SU:DAT
REPEATED
START
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 12 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 12 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 12 for
applicable timing.
Bit Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse
t
SU:STA
t
HD:STA
t
SP
t
SU:STO