DS1877T+T&R Maxim Integrated Products, DS1877T+T&R Datasheet - Page 25

• Manufacturer Part Number: DS1877T+T&R
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+T&R

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+TRL

The register maps show each byte/word (2 bytes) in
terms of its row in the memory. The first byte in the row
is located in memory at the row address (hexadecimal)
in the leftmost column. Each subsequent byte on the row
is one/two memory locations beyond the previous byte/
word’s address. A total of 8 bytes are present on each
row. For more information about each of these bytes, see
the corresponding register description.
The following section provides the device’s register defi-
nitions. Each register or row of registers has an access
descriptor that determines the password level required
to read or write the memory. Level 2 password is intend-
ed for the module manufacture access only. Level 1
password allows another level of protection for items
the end consumer wishes to protect. Many registers are
always readable, but require password access to write.
There are a few registers that cannot be read without
password access. The following access codes describe
each mode the device uses with factory settings for the
PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h)
registers.
ACCESS
<10/_>
<11/_>
CODE
<0/_>
<1/_>
<2/_>
<3/_>
<4/_>
<5/_>
<6/_>
<7/_>
<8/_>
<9/_>
than the rest of the row/byte, so look at each
Read not applicable
Read not applicable
At least 1 byte/bit in the row/byte is different
READ ACCESS
byte/bit separately for permissions.
Read PW2
Read PW1
Read PW2
Read PW2
Read all
Read all
Read all
Read all
Read all
Register Descriptions
Memory Map Access Codes
SFP Controller for Dual Rx Interface
Write not applicable
Write not applicable
also writes to these
WRITE ACCESS
device hardware
Write all, but the
Write PW2 +
Write PW2
Write PW1
Write PW2
Write PW2
Write PW1
bytes/bits
mode_bit
Write all
Write all
There are three separate I
A0h, A2h, and B2h. A2h and B2h are used to configure
and monitor two receivers. Receiver 1 is accessed using
A2h. Receiver 2 is accessed using B2h. Many of the reg-
isters in A2h and B2h are shared registers. These reg-
isters can be read and written from both A2h and B2h.
MEMORY
<M> or
<C> or
<D> or
<_/M>
CODE
<_/C>
<_/D>
Memory Addresses A0h, A2h, and B2h
A common memory location is used for
A2h and B2h device addresses. Reading
or writing to these locations is identical,
regardless of using A2h or B2h addresses.
Different memory locations are used for A2h
and B2h device addresses.
Mixture of common and different memory
locations for A2h and B2h device address-
es. See the individual bytes within the row
for clarification. If “M” is used on an indi-
vidual byte, see the expanded bit descrip-
tions to determine which bits are common
vs. different.
A2h AND B2h REGISTERS
2
C addresses in the device:
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