AMIS49587C5871RG ON Semiconductor, AMIS49587C5871RG Datasheet - Page 47

• Manufacturer Part Number: AMIS49587C5871RG
• Description: IC MODEM PLC 50/60MHZ 28PLCC
• Manufacturer: ON Semiconductor

Specifications of AMIS49587C5871RG

• Baud Rates: Selectable
• Interface: SCI
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Number Of Transmitters: 1
• Power Supply Requirement: Single
• Package Type: PLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Operating Temperature (max): 70C
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Lead Free Status / Rohs Status: Compliant

Status Message in MONITOR MODE:
Where:
Not SYNC
Not SET
Buffer BUSY
TS_Nb[2:0]
Alarm_EN
PLL_LOCK
DEP[2:0]
x
APPENDIX C: SUMMARY OF WRITECONFIG_REQUEST
STATUS MESSAGE IN SLAVE MODE
Table 39. WRITECONFIGNEW_REQUEST FOR MASTER MODE
First Initiator MAC Address (FIMA)
Last Initiator MAC Address (LIMA)
Local MAC
Address
Active Initiator Address
Time−out−synchro−confirm
Time−out−frame−not−ok
Time−out−not−addressed
Mac−group−addresses
Fs
Fm
R_ZC_ADJUST
NbAlarm
R_ALC_CTRL→Value
|Max_Transmistting_Gain→Value
R_ALC_CTRL→Value
Max_Transmistting_Gain→Mode
R_CONF_TX_DATA_PRE_SLOT_SEL
Pad
R_CONF→MODE
Byte
1
2
3
4
Content
Data 1
Data 2
Data 3
Start
Field
Indication of synchronization with mains
Indication is AMIS 49587 is set
Indication if PLC buffer is busy
Time slot counter
Alarm detection status
PLL lock status
Delta Electrical Phase
Not Used
Bit 7
0
x
TS_Nb[2:0]
DEP[2:0]
Bit 6
0
x
(b7 to b4)
(b3 to b1)
(b5 to b3)
1 bit (b0)
1 bit (b7)
1 bit (b6)
10 bytes
Length
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
2 bytes
1 byte
4 bits
3 bits
3 bits
Bit 5
http://onsemi.com
1
x
FIMA to LIMA
0000 to FFFF
0000 to FFFF
0000 to FFFF
00 to FF
Value
XXXX
XXXX
XXXX
XXXX
XXXX
XXXX
0000
0000
XXX
001
0
1
0
1
0
47
Bit 4
1
x
x
x
Structure
Don’t care
Don’t care
Master
Master
Don’t care
Slave: In seconds (Not used in Master mode)
Don’t care
Don’t care
Step Register for the Space Frequency Fs
Step Register for the Mark Frequency Fm
Value according to the voltage level of the 50 Hz
information for the input of the PLL.
Number of
Disable Phy Alarm functionality
Attenuation value in fixed mode
Automatic level control
Fixed mode
The output pin is the PRE_SLOT signal or Mode =
Master
The output pin is the transmitted DATA (for.Radio)
This bit is not used (adjust length at 1 byte)
Master mode for client station
Bit 3
1
x
x
x
repetitions of a Phy Alarm
Not SYNC
Bit 2
1
x
x
Description
Not SET
ALARM
Bit 1
_EN
1
x
_LOCK
BUSY
Buffer
Bit 0
PLL
1
x