LH79525N0Q100A1 NXP Semiconductors, LH79525N0Q100A1 Datasheet - Page 42
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LH79525N0Q100A1
Manufacturer Part Number
LH79525N0Q100A1
Description
Microcontrollers (MCU) LCD USB ETH'NET MMU
Manufacturer
NXP Semiconductors
Datasheet
1.LH79525N0Q100A1.pdf
(64 pages)
Specifications of LH79525N0Q100A1
Data Bus Width
32 bit
Program Memory Type
ROMLess
Data Ram Size
16 KB
Interface Type
I2C, I2S, IrDA, SSP, UART, USB
Maximum Clock Frequency
76.205 MHz
Number Of Programmable I/os
86
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
LQFP
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / Rohs Status
Details
Other names
LH79525N0Q100A1;55
Available stocks
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Manufacturer
Quantity
Price
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FREESCALE
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LH79525N0Q100A1,55
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Quantity:
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LH79524/LH79525
SDRAM MEMORY CONTROLLER WAVEFORMS
SDRAM Burst Read (page already open). Figure 22
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
42
Figure 21 shows the waveform and timing for an
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. SDCKE is HIGH.
SDRAMcmd
D[31:0]
A[14:0]
DQMx
SCLK
t SDCLK
Figure 21. SDRAM Burst Read
NXP Semiconductors
t OVXXX
Rev. 01 — 16 July 2007
t OVDQ
READ
COLUMN
BANK,
t OHXXX
t OVA
LATENCY = 2
NOP
CAS
tISD tIHD
NOP
DATA n
NOP
t OHDQ
DATA n + 1
READ
DATA n + 2
NOP
DATA n + 3
Preliminary data sheet
NOP
System-on-Chip
LH79525-3