ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 86

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ELLXT971ABE.A4

Manufacturer Part Number
ELLXT971ABE.A4
Description
IC TRANS 3.3V ETHERNET 64-BGA
Manufacturer
Intel
Type
PHY Transceiverr
Datasheet

Specifications of ELLXT971ABE.A4

Number Of Drivers/receivers
1/1
Protocol
IEEE 802
Voltage - Supply
3.14 V ~ 3.45 V
Mounting Type
Surface Mount
Package / Case
64-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
870479

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Intel
86
Figure 40. Intel
Table 42. Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Voltage threshold
Power Up delay
1. Typical values are at 25° C and are for design aid only, not guaranteed, and not subject to production
2. Power-up delay is specified as a maximum value because it refers to the PHY guaranteed performance.
testing.
The PHY comes out of reset after a delay of no more than 300 μ s. System designers should consider this
value as a minimum value. After threshold v1 is reached, the MAC should delay no less than 300 μ s before
accessing the MDIO port.
®
®
LXT971A Transceiver Power-Up Timing
Parameter
LXT971A Transceiver Power-Up Timing
MDIO, and
2
so on
VCC
Symbol
v1
t1
Min
v1
Typ
2.9
1
Max
300
t1
Units
μ s
B3494-01
V
Document Number: 249414-003
Revision Date: June 18, 2004
Test Conditions
Datasheet

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