ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 57

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

5.9
5.9.1
5.9.2
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Note: When the LXT971A Transceiver detects incorrect polarity for a 10BASE-T operation, Register bit
Monitoring Operations
Monitoring Auto-Negotiation
Auto-negotiation can be monitored as follows:
17.5 is set to ‘1’.
Monitoring Next Page Exchange
The LXT971A Transceiver offers an Alternate Next Page mode to simplify the next page exchange
process. Normally, Register bit 6.1 (Page Received) remains set until read. When Alternate Next
Page mode is enabled, Register bit 6.1 is automatically cleared whenever a new negotiation process
takes place. This action prevents the user from reading an old value in bit 6.1 and assuming that
Registers 5 and 8 (Partner Ability) contain valid information. Additionally, the LXT971A
Transceiver uses Register bit 6.5 to indicate when the current received page is the base page. This
information is useful for recognizing when next pages must be resent due to a new negotiation
process starting. Register bits 6.1 and 6.5 are cleared when read.
•
•
•
Register bit 17.7 is set to ‘1’ once the auto-negotiation process is completed.
Register bits 1.2 and 17.10 are set to ‘1’ once the link is established.
Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and
duplex).
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
57