ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 5

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

Figures
Datasheet
Document Number: 249414-003
Revision Date: 25-Oct-2005
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Ball Assignments for Intel
Pins for Intel
Management Interface Read Frame Structure ................................................... 30
Management Interface Write Frame Structure ................................................... 30
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Initialization Sequence for Intel
Hardware Configuration Settings .......................................................................38
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Clocking for 10BASE-T ...................................................................................... 42
Clocking for 100BASE-X .................................................................................... 42
Clocking for Link Down Clock Transition ............................................................ 43
Intel
100BASE-X Frame Format ................................................................................ 46
100BASE-TX Data Path .....................................................................................47
100BASE-TX Reception with No Errors ............................................................. 48
100BASE-TX Reception with Invalid Symbol ..................................................... 48
100BASE-TX Transmission with No Errors ........................................................ 49
100BASE-TX Transmission with Collision .......................................................... 49
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LED Pulse Stretching ......................................................................................... 59
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Typical Interface - Intel
Typical Interface - Intel
Typical Interface - Intel
Logic Translator.................................................................................................69
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PHY Identifier Bit Mapping ................................................................................. 91
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Sample LQFP Package - Intel
Sample Pb-Free (RoHS-Compliant) LQFP Package -
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Sample TPBGA Package - Intel
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LXT971A Transceiver Block Diagram ...................................................... 12
LXT971A Transceiver MII Interrupt Logic ................................................. 31
LXT971A Transceiver Link Establishment Overview ................................ 39
LXT971A Transceiver Loopback Paths ....................................................45
LXT971A Transceiver Protocol Sublayers ................................................ 50
LXT971A Transceiver Typical Twisted-Pair Interface - Switch.................. 63
LXT971A Transceiver Typical Twisted-Pair Interface - NIC ...................... 64
LXT971A Transceiver Typical Media Independent Interface.....................65
LXT971A Transceiver 100BASE-TX Receive Timing - 4B Mode ..............76
LXT971A Transceiver 100BASE-TX Transmit Timing - 4B Mode ............. 77
LXT971A Transceiver 100BASE-FX Receive Timing................................ 78
LXT971A Transceiver 100BASE-FX Transmit Timing............................... 79
LXT971A Transceiver 10BASE-T Receive Timing ................................... 80
LXT971A Transceiver 10BASE-T Transmit Timing .................................. 81
LXT971A Transceiver 10BASE-T Jabber and Unjabber Timing ..............82
LXT971A Transceiver 10BASE-T SQE (Heartbeat) Timing .....................83
LXT971A Transceiver Auto-Negotiation and Fast Link Pulse Timing........ 84
LXT971A Transceiver Fast Link Pulse Timing .......................................... 84
LXT971A Transceiver MDIO Input Timing................................................. 85
LXT971A Transceiver MDIO Output Timing .............................................. 85
LXT971A Transceiver Power-Up Timing ................................................... 86
LXT971A Transceiver RESET_L Pulse Width and Recovery Timing........ 87
LXT971A Transceiver PBGA Package Specification .............................. 105
LXT971A Transceiver LQFP Package Specifications ............................. 106
LXT971A Transceiver.............................................................................. 107
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LXT971A Transceiver 64-Pin LQFP Package ............................. 14
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LXT971ATransceiver to 3.3 V Fiber Transceiver......... 67
LXT971A Transceiver to 5 V Fiber Transceiver........... 68
LXT971A Transceiver to Triple PECL-to-PECL
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LXT971A Single-Port 10/100 Mbps PHY Transceiver
LXT971A Transceiver 64-Ball PBGA ...................... 13
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LXT971A Transceiver ..................................... 107
LXT971A Transceiver ..................................... 34
LXT971A Transceiver .................................. 108
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