ELLXT971ABE.A4 Intel, ELLXT971ABE.A4 Datasheet - Page 25

• Manufacturer Part Number: ELLXT971ABE.A4
• Description: IC TRANS 3.3V ETHERNET 64-BGA
• Manufacturer: Intel
• Type: PHY Transceiverr

Specifications of ELLXT971ABE.A4

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3.14 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 870479

5.1
5.1.1
5.1.2
Datasheet
Document Number: 249414-003
Revision Date: June 18, 2004
Note: The LXT971A Transceiver also supports 100BASE-FX operation through an LVPECL interface.
Device Overview
The LXT971A Transceiver is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps
and 100 Mbps networks. It complies with applicable requirements of IEEE 802.3. It directly drives
either a 100BASE-TX line or a 10BASE-T line.
Comprehensive Functionality
The LXT971A Transceiver provides a standard Media Independent Interface (MII) for 10/100
MACs. The LXT971A Transceiver performs all functions of the Physical Coding Sublayer (PCS)
and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X
standard. It also performs all functions of the Physical Media Dependent (PMD) sublayer for
100BASE-TX connections.
The LXT971A Transceiver reads its configuration pins on power-up to check for forced operation
settings.
If the LXT971A Transceiver is not set for forced operation, it uses auto-negotiation/parallel
detection to automatically determine line operating conditions. If the PHY device on the other side
of the link supports auto-negotiation, the LXT971A Transceiver auto-negotiates with it using Fast
Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT971A
Transceiver automatically detects the presence of either link pulses (10 Mbps PHY) or Idle
symbols (100 Mbps PHY) and sets its operating conditions accordingly.
The LXT971A Transceiver provides half-duplex and full-duplex operation at 100 Mbps and 10
Mbps.
Optimal Signal Processing Architecture
The LXT971A Transceiver incorporates high-efficiency Optimal Signal Processing (OSP) design
techniques, which combine optimal properties of digital and analog signal processing.
The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by
as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques
in the receive equalizer avoids the quantization noise and calculation truncation errors found in
traditional DSP-based receivers (typically complex DSP engines with A/D converters). This results
in improved receiver noise and cross-talk performance.
The OSP signal processing scheme also requires substantially less computational logic than
traditional DSP-based designs. This lowers power consumption and also reduces the logic
switching noise generated by DSP engines. This logic switching noise can be a considerable source
of EMI generated on the device’s power supplies.
The OSP-based LXT971A Transceiver provides improved data recovery, EMI performance, and
low power consumption.
Intel
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
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