MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 116

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

15–2
15.5
15.6
15.7
latching the data to BR3(7:4). Similarly, data to be transmitted in the Q channel of the TE is internally
latched from BR2(7:4) during the 47th baud of the transmitted INFO 3 in the 20th frame of a multiframe.
At this time, the received SC1 through SC5 subchannel nibbles is also made available. A mutiframing
interrupt is cleared by reading BR3. Reading BR3 clears the interrupt in both the NT and TE modes
of operation, regardless of whether the MC145574 is configured to generate an interrupt in the event
of a new nibble or every multiframe. Note that NR3(2) is a read only bit.
IRQ3
IRQ3 is provided to indicate a change in the received INFO state of the transceiver. In the NT mode,
this corresponds to a change in the receiving INFO 0, INFO 1, INFO 3, or INFO X state. Alternatively,
in the TE mode this corresponds to a change in the receiving INFO 0, INFO 2, INFO 4, or INFO X
state. Thus, when a change occurs in one of these states, the MC145574 internally sets NR3(3) to
a 1. If the IRQ3 ENABLE is set to 1, an interrupt to an external device will be generated. IRQ3 can
be cleared by writing a 0 to NR3(3). This bit is reset by a software reset or a hardware reset. Note
that the transmission states for the NT (INFO 0, INFO 2, and INFO 4) and for the TE (INFO 0, INFO 1,
and INFO 3) are as defined in Section 3. INFO X is defined as any transmission state other than those
states. An example of such a state would be when the MC145574 is programmed to transmit a 96 kHz
test signal (BR11(0) = 1). The MC145574 comes out of reset in the receiving “INFO X” state. Hence,
IRQ3 will be generated when it recognizes either INFO 0, INFO 1, INFO 2, INFO 3, or INFO 4. Note
that NR3(3) is a read/write bit.
As soon as INFO 0, INFO LOW (1 or 2), or INFO HIGH (3 or 4) is detected, an interrupt is generated.
If the INFO X state persists for > 8 ms, then an INFO X interrupt is generated.
IRQ6
The interrupt request condition IRQ6 is generated when the NT has detected a far–end code violation
(FECV). An FECV occurs when a multiframe incoming to the NT from the TE(s) contains one or more
illegal S/T line code violations. This interrupt is used to indicate to an NT when to send an FECV
layer 1 maintenance message to the TEs as defined in ANSI T1.605. When IRQ6 occurs, the
MC145574 internally sets NR3(1) to a 1. If the IRQ6 ENABLE is set to 1, an interrupt to an external
device will be generated. The interrupt condition is cleared by writing a 0 to NR3(1).
Note that this bit is maskable by means of NR4(1). This interrupt is applicable in the NT mode of opera-
tion and only when multiframing has been enabled.
GCI MODE
In GCI mode, a Monitor channel message is output by the MC145574 if an equivalent SCP interrupt
condition has occurred. This message must be enabled by writing to the NR4 register (via the Monitor
channel). The Monitor channel message that occurs in response to an interrupt condition contains
the content of NR3.
NR3(3)
NR4(3)
NR3(1)
NR4(1)
Freescale Semiconductor, Inc.
For More Information On This Product,
CHANGE IN Rx INFO STATE
ENABLE
NT : FAR-END CODE VIOLATION (FECV)
TE : NOT APPLICABLE
ENABLE
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DETECTION
MC145574
MOTOROLA