MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 111

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
13.2.1
13.2.2
TE Master Mode (TEM)
The TEM mode is the normal mode of operation for a TE. The two main operational features of TEM
mode are as follows.
The IDL2/GCI is a master of the digital interface. This means that the IDL2/GCI outputs the frame
sync and clock. The frame sync and clock are signals derived from the received S/T loop signal (i.e.,
timing is recovered from the received INFO transmitted by the NT and is used to generate the IDL2
signals so the TE end can operate synchronously with the NT).
The D channel access procedure outlined in the ANSI spec is enabled. This means that access to
the D channel is controlled via a set of rules designed to enable secure HDLC data transmission on
a shared channel, and provides a means for the TEM to recognize when collisions have occurred.
This operation is fully detailed in Section 11, D Channel Operation.
The three pins used to control the D channel access are DREQUEST, DGRANT, and CLASS.
TE Slave Mode (TES)
In TES mode, the IDL2/GCI interface operates in slave mode; i.e., the IDL2/GCI frame sync and clock
are inputs. This mode is intended for use in NT2 applications where the IDL2/GCI interface timing
is derived from a low jitter network synchronous source. The MC145574 has jitter/wander buffers which
absorb the clock/frame sync jitter and prevent data loss. The MC145574 will be able to absorb 60 s
peak–to–peak wander, which exceeds the 18 s peak–to–peak over 24 hours wander stated in Q.502.
There is no D channel contention circuitry in TES mode. The device has transparent access to the
D channel. It is intended that the TES operates in point–to–point applications only and thus does not
need D channel contention arbitration.
To facilitate the generation of the timing signals required by the slave IDL2/GCI interface, a pin is
provided which outputs a frame sync or a clock. These signals are synchronized to the received INFO
transmitted by the NT and can be used to provide network timing if no other source in the NT2 is
available. The choice of frame sync or clock and the frequency of the clock are all selectable via the
SCP.
The TFSC output is to allow the NT2 to be synchronized to the network. The TFSC is an 8 kHz frame
sync signal that is synchronized to the received network signal.
Alternatively, TFSC can be reprogrammed via the SCP to provide TCLK. TCLK is a clock, whose fre-
quency can be chosen via the SCP, which is also synchronized to the received S/T–interface. TCLK
can be used as an alternative to TFSC in NT2 slave–slave mode. The frequency of TCLK is selected
in the same manner as the DCL frequency is selected in the TE master mode.
In both the TFSC and TCLK cases, the output pin senses if a signal is present; and if not, the output
is enabled and the device outputs its signal. This allows the TES devices to have this pin wire OR’d
with only one of the active devices outputting the sync clock. For this function to work correctly, the
pin must have an external resistor connected to V DD I/O.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
BR13(5)
0
0
1
1
MC145574
BR7(2)
0
1
0
1
2.048 MHz
1.536 MHz
2.56 MHz
512 kHz
TCLK
13–5