MC145574AAC Freescale Semiconductor, MC145574AAC Datasheet - Page 105

• Manufacturer Part Number: MC145574AAC
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574AAC

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
12.5
12.6
12.7
12.8
12.9
READING Q CHANNEL DATA FROM AN NT-CONFIGURED MC145574
The Q data nibble received from the TE(s) is obtained by reading BR3(7:4). The demodulated Q chan-
nel data is written to this register every 5 ms. BR3(7:4) are read only bits.
WRITING Q CHANNEL DATA TO A TE-CONFIGURED MC145574
Data written to BR2(7:4) is transmitted in the Q channel. The TE–configured MC145574 polls this
internal register once every 5 ms (a multiframe is 5 ms in duration). If no new data has been written
to this register, the old data is re–transmitted. When multiframing is disabled, the data in this register
is ignored and the Fa bit obeys the multiframing wrapping criteria as outlined in CCITT I.430, ETSI
ETS 300012, and ANSI T1.605.
BR2(7:4) comes out of reset in the all–1s state in the TE mode of operation. To accommodate other
TEs on the loop, BR2(7:4) should be left in the all–1s state when the TE does not have access to
the Q channel.
MULTIFRAME INTERRUPTS IN A TE-CONFIGURED MC145574
The TE will generate an interrupt either once every multiframe or only in the event of a new SC1 sub-
channel nibble having been received. A new SC1 subchannel nibble is defined as one which differs
from the previous SC1 nibble. Table 12–3 illustrates how to configure a TE for either of these options.
READING S SUBCHANNEL DATA FROM A TE-CONFIGURED
MC145574
The S subchannel nibbles SC1, SC2, SC3, SC4, and SC5 received from the NT are obtained by reading
BR3(7:4), BR9(7:4), BR9(3:0), BR10(7:4), and BR10(3:0), respectively. The demodulated S subchan-
nel data is written to these registers every 5 ms. These registers are read only registers in the TE
mode of operation.
MULTIFRAMING IN GCI MODE
Multiframing can be enabled in GCI mode by writing/reading to BR7(5) via the Monitor channel.
Interrupt Every
Multiframe
BR3(2)
X
Freescale Semiconductor, Inc.
0
1
For More Information On This Product,
Table 12–3. TE Multiframe Interrupts
Go to: www.freescale.com
Enable Multiframing
Interrupt
NR4(2)
MC145574
0
1
1
Multiframing never causes an interrupt
An interrupt is generated on the reception of a
new SC1 subchannel nibble
An interrupt is generated every multiframe
MC145574
IRQ
12–3