Core1553BBC-SKT MICROSEMI, Core1553BBC-SKT Datasheet - Page 7

• Manufacturer Part Number: Core1553BBC-SKT
• Description: Programmable Logic Development Tools Bus Controller
• Manufacturer: MICROSEMI

Table 3 • Control and Status Signals
CPU Interface
The CPU interface allows access to the Core1553BBC internal registers and direct access to the backend memory. This
interface is synchronous to the clock
Table 4 • CPU Interface Signals
Name
CLK
RSTINn
INTOUT
MEMFAIL
BUSY
EXTFLAG
Name
CPUCSn
CPUWRn[1:0]
CPURDn
CPUWAITn
CPUMEM
CPUADDR[15:0]
CPUDOUT[15:0]
CPUDIN[15:0]
CPUDEN
Type
Type
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
In
In
In
Description
Master clock input (either 12 MHz, 16 MHz, 20 MHz, or 24 MHz)
Reset input (active low)
Interrupt Request (active high). The CPU is required to read the internal status register to find the
reason for the interrupt. It is cleared by the CPU writing to the interrupt register.
This goes high if the core fails to read or write data to the backend interface within the required
time. This can be caused by the backend not asserting MEMGNTn fast enough or asserting
MEMWAITn for too long. It is cleared by the CPU writing to the interrupt register.
This is high when the core is active, i.e. processing a message list.
External flag input used by the condition codes within the bus controller
Description
CPU chip select input (active low)
CPU write input (active low). Two write inputs are provided for processors that support byte
operations. When CPUWRn[1] is '0,' data bits [15:8] are written. When CPUWRn[0] is '0,' data bits
[7:0] are written.
CPU read input (active low)
CPU wait output (active low) indicates that the CPU should hold CPURDn or CPUWRn active while
the core completes the read or write operation. CPUWAITn is not asserted when the internal CPU
registers are accessed. When accessing the backend interface through the core, CPUWAIT will be
activated for a minimum of four clock cycles for read operations and three for write operations.
CPUWAITn is asserted for extra clock cycles if the backend interface delays asserting MEMGNTn or
asserts MEMWAITn.
Timing is shown in the
Selects whether the CPU accesses internal registers or backend memory.
'0': Accesses internal registers, register number is specified on CPUADDR[2:0]
'1': Accesses the backend memory
CPU address input
CPU data output
CPU data input
Data bus enable (active high). This signal is high when the core is providing data output on the
CPUDOUT bus. It is intended for a tristate enable function.
(Table
4).
Figure 12 on page 24
v4.0
and
Figure 13 on page
Core1553BBC MIL-STD-1553B Bus Controller
25.
7