Core1553BBC-SKT MICROSEMI, Core1553BBC-SKT Datasheet

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Core1553BBC-SKT

Manufacturer Part Number
Core1553BBC-SKT
Description
Programmable Logic Development Tools Bus Controller
Manufacturer
MICROSEMI
Datasheet
Core1553BBC MIL-STD-1553B Bus Controller
Product Summary
Intended Use
Key Features
Supported Families
Core Deliverables
© 2005 Actel Corporation
December 2005
• 1553B Bus Controller (BC)
• DMA Backend Interface to External Memory
• Supports MIL-STD-1553B
• Interfaces to External RAM
• Selectable Clock Rate of 12, 16, 20, or 24 MHz
• Provides Direct CPU Access to Memory
• Interfaces to Standard 1553B Transceivers
• Fully Automated Message Scheduling
• Fusion
• ProASIC3/E
• ProASIC
• Axcelerator
• RTAX
• SX-A
• RTSX-S
• Netlist Version
• RTL Version
– Supports up to 128kbytes of Memory
– Synchronous
– Backend Interface Identical to Core1553BRT
– Frame Support
– Conditional Branching and Sub-routines
– Variable Inter-message Gaps and RT Response
– Real Time Clock for Message Scheduling
– Asynchronous Message Support
– Compiled RTL Simulation Model, Compliant
– Compatible with the Actel Designer Place-and-
– VHDL or Verilog Core Source Code
Interface
Times
with the Actel Libero™ Integrated Design
Environment (IDE)
Route Tool
PLUS
or
Asynchronous
Backend
v 4 .0
Synthesis and Simulation Support
Verification and Compliance
Development System (Optional)
Contents
General Description ................................................... 2
Core1553BBC Device Requirements .......................... 4
Core1553BBC Verification and Compliance .............. 4
MIL-STD-1553B Bus Overview .................................... 4
I/O Signal Descriptions ............................................. 6
Bus Transceivers ........................................................ 20
Development System ............................................... 20
Typical BC System ..................................................... 22
Specifications ............................................................ 24
Ordering Information .............................................. 28
List of Changes ......................................................... 29
Datasheet Categories ............................................... 29
• Actel-Developed Testbenches, VHDL and Verilog
• Synthesis: Synplicity
• Simulation: Vital-Compliant VHDL Simulators and
• Actel-Developed Simulation Testbench
• Core Implemented on the 1553B BC Development
• Third-Party 1553B Compliance Testing of the
• Complete 1553B BC Implementation in an SX-A
• Includes a PCI Interface for Host CPU Connection
• Includes
– Synthesis Scripts
FPGA Compiler
OVI-Compliant Verilog Simulators
System
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
Device
Components
Transceivers
TM
/FPGA Express
®
, Synopsys
and
TM
®
(Design Compiler
Bus
), Exemplar
Termination
TM
®
1
/

Related parts for Core1553BBC-SKT

Core1553BBC-SKT Summary of contents

Page 1

... Complete 1553B BC Implementation in an SX-A Device • Includes a PCI Interface for Host CPU Connection • Includes Transceivers Components Contents General Description ................................................... 2 Core1553BBC Device Requirements .......................... 4 Core1553BBC Verification and Compliance .............. 4 MIL-STD-1553B Bus Overview .................................... 4 I/O Signal Descriptions ............................................. 6 Bus Transceivers ........................................................ 20 Development System ............................................... 20 Typical BC System ..................................................... 22 Specifications ............................................................ 24 Ordering Information .............................................. 28 List of Changes ......................................................... 29 Datasheet Categories ...

Page 2

... Data words are read from the memory Memory Glue Logic CPU Figure 1 • Typical Core1553BBC System BusA BusB Figure 2 • Core1553BBC BC Block Diagram 2 and transmitted on the 1553B bus. Data received is written to the memory. The core can be configured directly to connect to synchronous or asynchronous memory devices. Figure 1. ...

Page 3

... Core1553BBC MIL-STD-1553B Bus Controller directly access the memory connected to the backend interface. These features can simplify system design. The backend interface for the Core1553BBC allows a simple connection to a memory device. The backend interface can be configured to connect to either synchronous or asynchronous memory devices. This ...

Page 4

... Core1553BBC MIL-STD-1553B Bus Controller Core1553BBC Device Requirements The Core1553BBC can be implemented in several Actel FPGA devices. Core1553BBC implemented in these devices. Table 1 • Device Utilization Family Combinatorial Fusion ProASIC3/E PLUS ProASIC Axcelerator RTAX-S SX-A RTSX-S The Core1553BBC clock rate can be programmed to 12, 16, 20 MHz. All Actel device families listed in Table 1 easily meet this performance requirement ...

Page 5

... Gap Command BC Mode Message Next Data Gap Command BC RT Status Message Next Word Gap Command BC Next v4.0 Core1553BBC MIL-STD-1553B Bus Controller shows the message formats. BC Next Command BC Next Command RT2 Response Status Message Time Word Gap Command BC Message Next Gap Command ...

Page 6

... Core1553BBC MIL-STD-1553B Bus Controller Word Formats There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW). Each 20-bit word consists of a 3-bit sync pattern, 16 bits of data, and a parity bit Bit Sync RT Address DW Sync SW Sync RT Address Figure 5 • ...

Page 7

... EXTFLAG In External flag input used by the condition codes within the bus controller CPU Interface The CPU interface allows access to the Core1553BBC internal registers and direct access to the backend memory. This interface is synchronous to the clock Table 4 • CPU Interface Signals Name Type ...

Page 8

... Core1553BBC MIL-STD-1553B Bus Controller Backend Interface The backend interface supports both synchronous operation and asynchronous operation to backend devices. Synchronous operation directly supports the use of internal FPGA memory blocks. Asynchronous operation allows connection to standard external memory devices. Table 5 • Backend Signals Name ...

Page 9

... R 001 SETUP RW 010 LISTPTR RW 011 MSGPTR R 100 CLOCK RW 101 ASYNCPTR RW Core1553BBC MIL-STD-1553B Bus Controller (Table 7). 9.58µs 9.68µs 9.75µs 9.79µs 4.58µs 4.68µs 4.75µs 4.79µs Size Function [3:0] Allows the CPU to control the BC [15:0] Provides status information ...

Page 10

... Core1553BBC MIL-STD-1553B Bus Controller Table 8 • Bus Controller Registers Address Name Type 110 STACKPTR RW 111 INTERRUPT RW Table 9 • Setup Register Bits Name Type Reset 15 FORCEORUN RW 14 CLOCKEN RW 13:12 CLKFREQ RW 11 RETRYMODE WR 10 INTENABLE RW 9 AUTOCLOCK RW 8 AUTOSTACK RW 7:6 CLKRATE RW 5:4 IMG ...

Page 11

... Writing a '1' starts the bus controller. The bus controller cannot be started when an asynchronous message is active. Table 11 • Status Register Bits Name Type Function 15:8 VERSION R Indicates the Core1553BBC code revision Core release notes provide latest version numbers. 7:6 Reserved R Reserved, set LOOPFAIL R Indicates that a loopback failure occurred in the current frame ...

Page 12

... Core1553BBC MIL-STD-1553B Bus Controller Table 12 • Interrupt Register Bits Name Type Function 15 INTPENDING RW When set, the BC has an interrupt pending. This bit is set if any of the INTVECT bits are set. 14:8 INTVECT RW Interrupt Reason The CPU writing a '1' to the bit clears the bit. ...

Page 13

... PARAMETER Figure 6 • BC Memory Usage Instruction List The instruction list contains pairs of words: an instruction and a parameter. Core1553BBC supports a broad set of instructions allowing branching and sub-routine calls with condition code support. This allows complex instruction lists to be supported. The instruction contains a 4-bit OPCODE and a 5-bit condition code field ...

Page 14

... Core1553BBC MIL-STD-1553B Bus Controller Table 14 • Supported Instructions (Continued) OPCODE Function Condition Code Parameter 0110 LOADC Yes 0111 WAITC Yes 1000 CALL Yes 1001 RET Yes 1010 RETAS Yes 1011 STOREF Yes Others Illegal N/A Table 15 • Condition Codes Condition Code Function Description ...

Page 15

... Performs the instruction if asynchronous message processing is not active 11101 NEXT Performs the instruction if the External flag input is inactive '0' 11110 NSFLAG Performs the instruction if the previously stored flag bit was not set Others 0xxxx Illegal Equivalent to NEVER Others 1xxxx Illegal Equivalent to ALWAYS Core1553BBC MIL-STD-1553B Bus Controller v4.0 15 ...

Page 16

... Core1553BBC MIL-STD-1553B Bus Controller Message Block An 8-word message block controls each message. The BC reads the 1553B command words from the message block and will write the received status words back to message block. Message blocks must be positioned on an 8-word memory boundary (Table 16). Table 16 • ...

Page 17

... Unexpected bit set in the status word 7 Got the RT-to-RT RX status word 6 Got the status word, for RT-to-RT got the TX status word 5:0 Number or data words transmitted or received. Note: '000000' indicates 0 and '100000' indicates 32 15:0 Not Used v4.0 Core1553BBC MIL-STD-1553B Bus Controller 17 ...

Page 18

... Core1553BBC MIL-STD-1553B Bus Controller Detailed Operation Flow Table 17 shows the operations the core goes through in processing a message list containing two messages. The first message is a BC-to-RT transfer of three words, and the second is an RT-to-BC transfer of three words. Table 17 • Typical Operation ...

Page 19

... Error Conditions Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible (Table 18). Table 18 • Error Conditions Error Condition Group Error Signaling 1553B signaling error, parity, Manchester error, too many or to few words, or incorrect SYNC type 1553B Loopback Failure. Can occur responds ...

Page 20

... On detecting an error that can be retried, the BC immediately retries the message. Each message can be retried up to six times. The Core1553BBC can be programmed to retry up to three times on the original bus, then retry up to three times on the alternative bus simply retry initially on the alternative bus and then switch buses after each attempt ...

Page 21

... Memory 64K*16 PCI Interface Development PCB Figure 7 • Core1553BBC Development System Core1553BBC MIL-STD-1553B Bus Controller Memory Access PCI Target Interface Core1553BBC Actel FPGA v4.0 Pulse Transformer Pulse Transceiver Transformer 21 ...

Page 22

... Core1553BBC MIL-STD-1553B Bus Controller Typical BC System Core1553BBC requires a master CPU to set up the data tables. The CPU needs to be able to access the internal core registers as well as the backend memory. Core1553BBC can be configured in two ways with the CPU shared memory and with its own memory. ...

Page 23

... Memory Bus Arbritator CPU Figure 9 • Core1553BBC Using Shared Memory Core1553BBC MIL-STD-1553B Bus Controller BUSAINEN RCVSTBA BUSAINP RXDAIN BUSAINN RXDAIN BUSAOUTINH TXINHA BUSAOUTP TXDAIN BUSAOUTN TXDAIN Transceiver BUSBINEN RCVSTBA BUSBINP RXDBIN BUSBIN RXDBIN BUSAOUTINH TXINHA BUSBOUTP TXDBIN BUSBOUTN TXDBIN Core1553BBC Actel FPGA v4 ...

Page 24

... Core1553BBC MIL-STD-1553B Bus Controller Specifications CPU Interface Timing CPUCSN CPURDN CPUADDR CPUMEM CPUDOUT CPUDEN CPUWAITN Figure 10 • CPU Interface Register Read Cycle CLK CPUCSN CPUWRN[1:0] CPUADDR CPUMEM CPUDIN CPUWAITN Figure 11 • CPU Interface Register Write Cycle CLK CPUCSN CPURDN CPUADDR CPUMEM ...

Page 25

... Data Write Tpd Tpd The CPU interface signals are internally synchronized to the Core1553BBC master clock. If these inputs are asynchronous, then CPUCSn, CPUADDR, and CPUDATA should be valid/invalid before CPUWRn, and remain valid after CPUWRn. CPUWRn must be active for at least one clock cycle. ...

Page 26

... Core1553BBC MIL-STD-1553B Bus Controller CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 16 • Asynchronous Memory Write Cycle CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR MEMDIN MEMWAITn Figure 17 • Synchronous Memory Read Cycle CLK MEMREQn MEMGNTn MEMCEN MEMDEN ...

Page 27

... Figure 19 • Synchronous Memory Read Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 20 • Synchronous Memory Write Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn/WRn MEMWAITn MEMFAIL Figure 21 • Memory Grant Time-out Core1553BBC MIL-STD-1553B Bus Controller Tsu Timeout v4.0 27 ...

Page 28

... MEMFAIL Figure 22 • Memory Wait Time-out Clock Requirements To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12, 16, 20 MHz with a tolerance of ±0.01%. Ordering Information Core1553BBC can be ordered through your local Actel sales representative. It should be ordered using the following number scheme: Core1553BBC-XX, where XX is Table 19 • ...

Page 29

... This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Core1553BBC MIL-STD-1553B Bus Controller has been updated to include Fusion. has been updated to include ProASIC3/E. v4.0 ...

Page 30

Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation Actel Europe Ltd. 2061 Stierlin Court Dunlop House, Riverside Way Mountain View, CA Camberley, Surrey GU15 3YL 94043-4655 ...

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