Core1553BBC-SKT MICROSEMI, Core1553BBC-SKT Datasheet - Page 22

• Manufacturer Part Number: Core1553BBC-SKT
• Description: Programmable Logic Development Tools Bus Controller
• Manufacturer: MICROSEMI

Typical BC System
Core1553BBC requires a master CPU to set up the data
tables. The CPU needs to be able to access the internal
core registers as well as the backend memory.
Core1553BBC can be configured in two ways with the
CPU shared memory and with its own memory.
When configured with its own memory, only the CPU
port needs to be connected to the CPU. The CPU accesses
the
configuration also supports using an internal FPGA
Figure 8 • Core1553BBC with Its Own Memory
2 2
Core1553BBC MIL-STD-1553B Bus Controller
backend
memory
Memory
CPU
via
Core1553BBC.
Actel FPGA
Core1553BBC
BUSAOUTINH
BUSAOUTINH
BUSAOUTN
BUSBOUTN
BUSAOUTP
BUSBOUTP
This
BUSAINEN
BUSBINEN
BUSAINN
BUSAINP
BUSBINP
BUSBIN
v4.0
memory connected to the core and removes the need for
external bus arbitration on the CPU bus.
Alternatively, the core can share the CPU memory as
shown in
backend memory and CPU interfaces are connected to
the CPU bus. The core provides control lines that allow
the memory and CPU interfaces to share the same top-
level I/O pins. When in this configuration, the core needs
to read or write the memory it uses MEMREQn and
MEMGNTn signals to arbitrate for the CPU bus before
completing the cycle.
RCVSTBA
RXDAIN
RXDAIN
TXINHA
TXDAIN
TXDAIN
RCVSTBA
RXDBIN
RXDBIN
TXINHA
TXDBIN
TXDBIN
Figure 9 on page
Transceiver
Transformer
Transformer
Pulse
23. In this case, both the
Pulse