MT46H8M16LFBF-6:K Micron Technology Inc, MT46H8M16LFBF-6:K Datasheet - Page 51

• Manufacturer Part Number: MT46H8M16LFBF-6:K
• Description: IC SDRAM 128MB 166MHZ 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr
• Series: -r

Specifications of MT46H8M16LFBF-6:K

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 6.5/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 80mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 60-VFBGA
• Lead Free Status / Rohs Status: Compliant

Table 19: Burst Definition Table (Continued)
CAS Latency
PDF: 09005aef8331b3e9
128mb_mobile_ddr_sdram_t35m.pdf - Rev. F 03/10 EN
Length
Burst
Starting Column Address
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ
command and the availability of the first output data. The latency can be set to 2 or 3
clocks, as shown in Figure 18 (page 52).
For CL = 3, if the READ command is registered at clock edge n, then the data will be
nominally available at (n + 2 clocks +
tered at clock edge n, then the data will be nominally available at (n + 1 clock +
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5
7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E
Type = Sequential
51
128Mb: x16, x32 Mobile LPDDR SDRAM
Order of Accesses Within a Burst
t
AC). For CL = 2, if the READ command is regis-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Standard Mode Register
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F
1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E
2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D
3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C
4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B
5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A
6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9
7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8
8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7
9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6
A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5
B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4
C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3
D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2
E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1
F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0
Type = Interleaved
© 2007 Micron Technology, Inc. All rights reserved.
t
AC).