STM32W108HBU61TR STMicroelectronics, STM32W108HBU61TR Datasheet - Page 89

• Manufacturer Part Number: STM32W108HBU61TR
• Description: 16/32-BITS MICROS
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32W108HBU61TR

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: IEEE 802.15.4 Wireless
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 1.18V
• Operating Supply Voltage (typ): 1.25V
• Operating Supply Voltage (max): 1.32V
• Package Type: VFQFPN EP
• Pin Count: 40
• Mounting: Surface Mount
• Rad Hardened: No
• Core Processor: ARM® Cortex-M3™
• Program Memory Type: FLASH (128 kB)
• Controller Series: STM32W
• Ram Size: 8K x 8
• Interface: I²C, SPI, UART/USART
• Number Of I /o: 18
• Voltage - Supply: 1.18 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Compliant

STM32W108CB, STM32W108HB
9.8
9.8.1
31
15
30
14
Bits [1:0] SC_MODE: Serial controller mode.
●
●
A DMA buffer's end address, SCx_TXENDA/B (or SCx_RXENDA/B), can be written while
the buffer is loaded or active. This is useful for receiving messages that contain an initial
byte count, since it allows software to set the buffer end address at the last byte of the
message.
As the DMA channel transfers data between the transmit or receive FIFO and a memory
buffer, the DMA count register contains the byte offset from the start of the buffer to the
address of the next byte that will be written or read. A transmit DMA channel has a single
DMA count register (SCx_TXCNT) that applies to whichever transmit buffer is active, but a
receive DMA channel has two DMA count registers (SCx_RXCNTA/B), one for each receive
buffer. The DMA count register contents are preserved until the corresponding buffer, or
either buffer in the case of the transmit DMA count, is loaded, or until the DMA is reset.
The receive DMA count register may be written while the corresponding buffer is loaded. If
the buffer is not loaded, writing the DMA count register also loads the buffer while
preserving the count value written. This feature can simplify handling UART receive errors.
The DMA channel stops using a buffer and unloads it when the following is true:
Typically a transmit buffer is unloaded after all its data has been sent, and a receive buffer is
unloaded after it is filled with data, but writing to the buffer end address or buffer count
registers can also cause a buffer to unload early.
Serial controller DMA channels include additional features specific to the SPI and UART
operation and are described in those sections.
Serial controller registers
Serial mode register (SCx_MODE)
Address offset: 0xC854 (SC1_MODE) and 0xC054 (SC2_MODE)
Reset value:
29
13
Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET
register.
Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or
SC_RXLODA/B) bits in the SCx_DMACTRL register.
(DMA buffer start address + DMA buffer count) > DMA buffer end address
0: Disabled.
1: UART mode (valid only for SC1).
28
12
27
11
0x0000 0000
26
10
25
9
Reserved
Doc ID 16252 Rev 8
24
8
Reserved
23
7
22
6
2: SPI mode.
3: I
2
C mode.
21
5
20
4
19
3
Serial interfaces
18
2
17
SC_MODE
1
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