STM32F101RDT6TR STMicroelectronics, STM32F101RDT6TR Datasheet - Page 80
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STM32F101RDT6TR
Manufacturer Part Number
STM32F101RDT6TR
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F101RET6.pdf
(106 pages)
Specifications of STM32F101RDT6TR
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
36MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F101RDT6TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical characteristics
5.3.14
80/106
Figure 39. I/O AC characteristics definition
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under ambient temperature and V
Table
Table 48.
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
Figure 40. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
V
V
V
V
V
NF(NRST)
IH(NRST)
IL(NRST)
Symbol
F(NRST)
hys(NRST)
the series resistance must be minimum
Table
R
10.
PU
48. Otherwise the reset will not be taken into account by the device.
(1)
(1)
(1)
(1)
PU
External
reset circuit
NRST pin characteristics
(see
NRST Input low level voltage
NRST Input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
NRST Input filtered pulse
NRST Input not filtered pulse
EXT ERNAL
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) 2/3)T and if the duty cycle is (45-55%)
Table
(1)
0.1 µF
Parameter
45).
t r(I O)out
NRST
Doc ID 14610 Rev 7
(2)
(~10% order)
10%
V DD
50%
when loaded by 50pF
R PU
90%
.
(2)
STM32F101xC, STM32F101xD, STM32F101xE
DD
Conditions
supply voltage conditions summarized in
V
IN
T
10%
Table 48
V
50%
SS
Filter
90%
t r(I O)out
STM32F10xxx
–0.5
Min
300
are derived from tests
IL(NRST)
30
Internal Reset
2
max level specified in
Typ
200
40
V
ai14132c
DD
Max
100
0.8
50
+0.5
ai14131
Unit
to
mV
k
ns
ns
V