DLP-2232H DLP Design Inc, DLP-2232H Datasheet - Page 10

• Manufacturer Part Number: DLP-2232H
• Description: Interface Modules & Development Tools Dual Ch USB Adapter w/ FTDI FT2232H
• Manufacturer: DLP Design Inc
• Series: -r

Specifications of DLP-2232H

• Interface Type: USB, I2C, JTAG, SPI, UART
• Description/function: High Speed USB Adapter
• Dimensions: 57.8 mm x 23.5 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2
• Product: Interface Modules
• Supply Current: 75 mA
• Supply Voltage (max): 5 V
• Supply Voltage (min): 4 V
• Main Purpose: Interface, USB 2.0 to UART (RS232) Bridge
• Embedded: No
• Utilized Ic / Part: FT2232H
• Primary Attributes: Full Speed USB to High-Speed UART
• Secondary Attributes: Royalty-Free Drivers, 2K EEPROM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.0 PIN USAGE EXAMPLES
The following tables highlight two possible configurations for the DLP-2232H module. There are
numerous additional combinations available. For the complete DLP-2232H pin list refer to the
pin descriptions in section 2.0.
Rev. 1.1 (May 2011)
P
P
I
10
11
12
13
14
15
19
20
I
N
N
1
2
3
4
5
6
7
8
9
#
#
CASE 1: Port A: 245 FIFO Synchronous, Port B 245 FIFO Asynchronous
P
S
SIWUB –The Port B Send Immediate / WakeUp signal combines two functions on a
single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in
the EEPROM, strobing this pin low will cause the device to request a resume on the USB
Bus. Normally, this can be used to wake up the Host PC. During normal operation
(PWREN# = 0), if this pin is strobed low any data in the device TX buffer will be sent out
over USB on the next Bulk-IN request from the drivers regardless of the pending packet
size. This can be used to optimize USB transfer speed for some applications. Tie this pin
to VCCIO if not used.
PORT B WR# - When taken from a high to a low state, WR reads the 8 data lines and
writes the byte into the FIFO’s transmit buffer. Data written to the transmit buffer is sent
to the host PC within the TX buffer timeout value (default 16mS) and placed in the buffer
that was created when the USB port was opened.
PORT B RD# - When pulled low, RD# takes the 8 data lines from a high-impedance
state to the current byte in the FIFO’s buffer. Taking RD# high returns the data pins to a
high- impedance state and prepares the next byte (if available) in the FIFO to be read.
PORT B TXE# - Transmit Buffer Empty: When high, do not write data into the FIFO.
When low, data can be written into the FIFO by toggling WR. During reset this signal pin
is tri-state. Data is latched into the FIFO on the falling edge of the WR pin.
PORT B RXF# - Receive Buffer Full : When low, at least 1 byte is present in the FIFO’s
receive buffer and is ready to be read with RD#. RXF# goes high when the receive buffer is
empty. During reset this signal pin is tri-state. If the Remote Wakeup option is enabled in the
internal EEPROM, during USB Suspend Mode (PWREN#=1) RXF# becomes an input. This can
be used to wake up the USB host from Suspend Mode by strobing this pin low for a minimum of
20ms which will cause the device to request a resume on the USB bus.
PORT B DB7 – Port B FIFO Data Bus Bit 7
PORT B DB6 – Port B FIFO Data Bus Bit 6
PORT B DB5 – Port B FIFO Data Bus Bit 5
PORT B DB4 – Port B FIFO Data Bus Bit 4
PORT B DB3 – Port B FIFO Data Bus Bit 3
PORT B DB2 – Port B FIFO Data Bus Bit 2
PORT B DB1 – Port B FIFO Data Bus Bit 1
PORT B DB0 – Port B FIFO Data Bus Bit 0
GROUND
GROUND
EXTVCC - Use for applying main power (4.5 to 5.25 volts) to the module. Connect to
PORTVCC if the module is to be powered by the USB port (typical configuration).
PORTVCC - Power from the USB port. Connect to EXTVCC if the module is to be
powered by the USB port (typical configuration). 500mA is the maximum current
available to the USB adapter and target electronics if the USB device is configured for
high power.
P
S
O
I
O
I
G
G
R
R
N
N
T
T
A
A
A
A
L
L
P
U
P
U
A
A
S
S
R
A
R
A
A
G
A
G
L
L
E
E
L
L
D
D
E
E
E
E
L
L
S
S
S
S
C
C
Y
Y
R
R
N
N
I
I
P
C
P
C
T
T
,
,
I
P
I
P
O
O
O
O
N
N
R
R
T
T
10
B
B
P
P
A
A
R
R
A
A
L
L
L
L
E
E
L
L
A
A
S
S
Y
Y
N
N
C
C
© DLP Design, Inc.