TP3410J National Semiconductor, TP3410J Datasheet - Page 7

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
2 2 Line Transmit Section
Data to be transmitted to the line consists of the customer’s
2B
processor plus other ‘‘spare’’ bits in the overhead chan-
nels This data is multiplexed and scrambled prior to addi-
tion of the syncword A pulse waveform synthesizer then
drives the transmit filter which in turn passes the line signal
to the line driver The differential line-driver outputs Lo
and Lo
external termination circuit A 1 1 5 transformer designed
as shown in the Applications section results in a signal am-
plitude of nominally 2 5V pk on the line for single quats of
the outer (
RDS accumulation of the 2B1Q line code continuous ran-
dom data will produce signal swings considerably greater
than this on the line Short-circuit protection is included in
the output stage overvoltage protection must be provided
externally
2 3 Line Receive Section
The receive input signal should be derived from the trans-
former by means of a coupling circuit as shown in the Appli-
cations section At the front-end of the receive section is a
continuous filter followed by a switched-capacitor low-pass
filter which limits the noise bandwidth A Hybrid Balance
Filter provides a degree of analog echo-cancellation in or-
der to limit the dynamic range of the composite signal An
A D converter then samples the composite received signal
prior to the cancellation of the ‘‘echo’’ from the local trans-
mitter by means of an adaptive digital transversal filter (i e
the ‘‘echo-canceller’’) Following this the attenuation and
distortion (inter-symbol interference) of the received signal
from the far-end caused by the transmission line are equal-
ized by a second adaptive digital filter configured as a Deci-
sion Feedback Equalizer (DFE) thereby restoring a ‘‘flat’’
channel response with maximum received eye opening over
a wide spread of cable attenuation characteristics
From the received line signal a Timing Recovery circuit
based on a DPLL (Digital Phase-Locked Loop) recovers a
low-jitter clock for optimum sampling of the received sym-
bols The MCLK input provides the reference clock for the
DPLL at 15 36 MHz Received data is then detected with
automatic correction for line signal polarity if necessary and
a flywheel synchronization circuit searches for and locks
onto the frame and superframe syncwords Frame lock will
be maintained until errored sync words are detected for
a
D channel data and the data from the maintenance
b
are designed to drive a transformer through an
g
3) levels Note however that because of the
(Continued)
FIGURE 2 Superframe Sync Pin Timing
a
7
480 ms If a loss-of-sync condition persists for 480 ms the
device will cease transmitting and go into a RESET state
While the receiver is synchronized data is descrambled us-
ing the specified polynomial and the individual channels de-
multiplexed and passed to their respective processing cir-
cuits
Whenever the loop is deactivated either powered up or
powered down a Line Signal Detect circuit is enabled to
detect the presence of an incoming 10 kHz wake-up tone if
the far-end starts to activate the loop The LSD circuit gen-
erates an interrupt and if the device is powered down pulls
the LSD pin low either of these indicators may be used to
alert an external controller which must respond with the
appropriate commands to initiate the activation sequence
(see the Activation section)
3 0 ACTIVATION CONTROL OVERVIEW
The TP3410 contains an automatic sequencer for the com-
plete control of the start-up activation sequence specified in
the ANSI standard Both the ‘‘cold-start’’ and the fast
‘‘warm-start’’ are supported Interaction with an external
controller requires only Activate Request and Deactivate
Request commands with the option of inserting breakpoints
in the sequence for additional external control if desired
Automatic control of the ‘‘act’’ and ‘‘dea’’ bits in the M4 bit
positions is provided along with the specified 40 ms and
480 ms timers used during deactivation A 15 second de-
fault timer is also included to prevent system lock-up in the
event of a failed activation attempt Section 11 gives an
overview of the activation handshake between the TP3410
and the controller See TP3410 User’s Manual AN-913 for
additional information
4 0 MAINTENANCE FUNCTIONS OVERVIEW
4 1 M Channel Processing
In each frame of the superframe there are 6 ‘‘Overhead’’
bits assigned to various control and maintenance functions
of the DSL Some processing of these bits may be pro-
grammed via the Command Registers while interaction with
an external controller provides the flexibility to take full ad-
vantage of the maintenance channels New data written to
any of the overhead bit Transmit Registers is resynchroniz-
ed internally to the next available complete superframe or
half-superframe as appropriate In addition the SFS pin
may be used to indicate the start of each superframe in 1
direction see Figure 2 and Register CR2
TL H 9151 – 26