TP3410J National Semiconductor, TP3410J Datasheet

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... Alternatively the GCI (General Circuit Interface) may be se- lected in which the 2B D data is multiplexed together with a control spare bits and loop maintenance data on 4 pins Combo and TRI-STATE are registered trademarks of National Semiconductor Corporation MICROWIRE trademark of National Semiconductor Corporation The General Circuit Interface ( interface specification of the Group-of-Four Euro- ...

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... CMOS 15 36 MHz syn- chronous clock output which is frequency- locked to the received line signal (unlike the XTAL pins it is not free-running) Pin Names for GCI Mode TL H 9151– 2 Order Number TP3410J See NS Package Number J28A Pin Symbol No 22 TSFS ...

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Pin Descriptions (Continued) PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE ONLY ( Pin Symbol Description Receive 2B1Q signal differential inputs from the line transformer For normal full- b duplex operation these pins should ...

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Pin Descriptions (Continued) Pin Symbol Description The digital input for multiplexed B D and control data clocked by BCLK at the rate of 1 data bit per 2 BCLK cycles and 32 data bits per 8 kHz ...

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Functional Description 1 1 Power-On Initialization When power is first applied power-on reset circuitry initializ- es the TP3410 and puts it into the power-down state in which all the internal circuits including the Master oscillator are inactive and in a ...

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Functional Description (Continued) Framing Quat Positions 1–9 Bit Positions 1–18 Superframe Basic Frame Sync Word 1 1 ISW ISW Framing Quat Positions 1–9 ...

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Functional Description (Continued Line Transmit Section Data to be transmitted to the line consists of the customer’ channel data and the data from the maintenance a processor plus other ‘‘spare’’ bits in the overhead chan- nels ...

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Functional Description (Continued Embedded Operations Channel The EOC channel consists of 2 complete 12-bit messages per superframe distributed through the M1 M2 and M3 bits of each half-superframe as shown in Table I Each message is composed of ...

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Functional Description (Continued) Format 2 Format 2 is the IDL in which the 2B transfer is assigned to the first 19 bits of the frame on the Bx and Br pins Channels are as- signed as follows B1 (8 bits) ...

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Functional Description (Continued) Transmit slots are numbered relative to FSa and receive slots relative to FSb Shown with examples of offset frames and Time-slot Assignments FIGURE 3-3 DSI Format 3 (Time-Slot Assignment) Slave Mode FSa defines B1 channel for Tx ...

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Functional Description (Continued Relationship To Data (Microwire Mode) For applications on a line-card in DSI Slave Mode the B and D channel slots can be interfaced to a Time-Division Multiplexed (TDM) bus and assigned to a time-slot ...

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Functional Description (Continued) Shown with example of Time-slot Assignment and FS a FIGURE 5 D-Port Interface Timing Using BCLK 7 0 MICROWIRE CONTROL PORT (MW e When Format used control information and maintenance channel ...

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Functional Description (Continued) The TP3410 has an enhanced MICROWIRE port such that it can connect to standard MICROWIRE master devices (such an NSC’s HPC and COP families) as well as the SCP (serial control port) interface master from the Motorola ...

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Functional Description (Continued GCI Frame Structure Figure 7 shows the frame structure at the GCI interface One GCI channel supports one TP3410 using a bandwidth of 256 kbit s consisting of the following channels multi- plexed together in ...

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Functional Description (Continued) Byte 1 (Register Address) Function Operation (NOP Write OPR Readback OPR Write CR1 Readback CR1 Write CR2 0 ...

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Functional Description (Continued) Byte 1 (Register Address) Function READABLE CONFIGURATION REGISTERS Default (No Change Write Cycle) OPR Contents CR1 Contents CR2 Contents ...

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Functional Description (Continued COMMAND REGISTER FUNCTIONS All addressing and bit-level functions are the same for both the Microwire and GCI Monitor Channels except where not- ed Register addresses are listed in Table II An asterisk indicates the Power-on ...

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Functional Description (Continued) mode and the 2B D slots at the receive digital interface a port(s) are in the high impedance state BP1 Not Used This bit is not used and should always be set to zero BP1 0 e ...

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Functional Description (Continued) RFS Remote Febe Select RFS 1 (default state) e The state of the outgoing bit is computed based on the state of the TFB (bit 1) in TXM56 register The TFB blt is set by the software ...

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Functional Description (Continued) Byte DR5 DR4 DR3 DR2 DR1 DR0 At Power-On Reset this register is initialized Receive D Channel Time-Slot Assignment Select DR5–DR0 SR1–SR0 DR5 –DR0 bits define the ...

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Functional Description (Continued Transmit M5 M6 Spare Bits Register TXM56 (Write Only) Byte LEC M51 M61 M52 At Power-On Reset and each time the device is Deactivat- ed (or ...

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Functional Description (Continued) The RXM4 Register consists of 8 bits which correspond to the M4 overhead bit position in each of the 8 Basic Frames of a superframe When the line is fully superframe synchro- nized the device extracts from ...

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Functional Description (Continued) FA0 This command may be used on a fully activated line to force the transmit ‘‘act’’ bit loss or denial transparency to the NT a (LT state J7) To revert back to sending ‘‘act’’ ...

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Functional Description (Continued) Deactivation is initiated by writing the DR command in the Activation Control Register causing ‘‘dea’’ e mitted towards the NT When the NT ceases to transmit confirmation of deactivation is provided Status indi- cator ...

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Applications Information (Continued) Note matching may be required to meet the longitudinal balance specification depending on the Longitudinal impedance to ground of the line interface The 15 and 1k resistors in the line interface circuit should be ...

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... preliminary and parameter limits are not indicative of characterization data with respect to power supply or temperature varia- tions Please contact your National Semiconductor Sales Office for the most current product information Symbol Parameter DIGITAL INTERFACES V Input Low Voltage ...

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Timing Characteristics Symbol Parameter FMCK Master Clock Frequency Master Clock Tolerance MCLK XTAL Input Clock Jitter tMH Clock Pulse Width tML Hi Low for MCLK tMR Rise and Fall Time tMF of MCLK DIGITAL INTERFACE ( Figures 11 12 and ...

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Timing Characteristics (Continued) Symbol Parameter MICROWIRE CONTROL INTERFACE (see Figure 14 ) tCH CCLK High Duration tCL CCLK Low Duration tSIC Setup Time CI Valid to CCLK High tHCI Hold Time CCLK High to CI Invalid tSSC Setup Time from ...

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Timing Diagrams FIGURE 11 Non-Delayed Data Timing Mode (Formats 1 and 3) FIGURE 12 Delayed Data Timing Mode (Formats 1 2 and 9151 – 28 (Shown with TS0 Selected 9151 – ...

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Timing Diagrams (Continued) Note output (GCI Master high for 8 bit intervals (16 BCLK cycles input (GCI Slave FIGURE 14a TP3410 Enhanced MICROWIRE Control Port Timing FIGURE 13 GCI and Format ...

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Timing Diagrams (Continued) FIGURE 14b TP3410 Normal MICROWIRE CLOCK Format FIGURE 14c TP3410 Alternate MICROWIRE CLOCK Format 9151 – 9151 – 30 ...

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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Ceramic Dual-In-Line Package (J) Order Number TP3410J NS Package Number J28A 2 A critical component is any component of a life ...