TP3410J National Semiconductor, TP3410J Datasheet - Page 12
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TP3410J
Manufacturer Part Number
TP3410J
Description
Manufacturer
National Semiconductor
Datasheet
1.TP3410J.pdf
(32 pages)
Specifications of TP3410J
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Not Compliant
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Quantity
Price
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Functional Description
Shown with example of Time-slot Assignment and FS
7 0 MICROWIRE CONTROL PORT (MW
When Format 1 2 3 or 4 is used control information and
maintenance channel data is written into and read back
from the TP3410 via the Microwire port consisting of the
control clock CCLK the serial data input CI and output
CO the Chip Select input CS and the interrupt output INT
The MW pin must be tied high to enable this port and the
port may be used regardless of whether the device is pow-
ered up or down Figures 6 and 14 show the timing which is
compatible with the Microwire port on the HPC and COPs
families of microcontrollers and Tables II and III list the con-
trol functions and status indicators
All read and write operations require 2 contiguous bytes As
shown in Tables II and III the first byte is the register ad-
FIGURE 5 D-Port Interface Timing Using BCLK
(Continued)
e
a
1)
e
FS
b
FIGURE 5-1 Format 1
FIGURE 5-2 Format 2
FIGURE 5-3 Format 3
12
dress and the second byte is the data byte Status Registers
request service under control of the Interrupt Stack with the
priority order listed in Table III
To shift data to and from the TP3410 CCLK must be pulsed
high 16 times while CS is low Data on the CI input is shifted
into the serial input register on the rising edge of each CCLK
pulse simultaneously data is shifted out from CO on each
falling edge of CCLK Bit 7 of byte 1 is shifted first CS must
return high at the end of the 2nd byte after which the con-
tents of the input shift register are decoded and the data is
loaded into the appropriate programmable register Pulling
CS low also clears the INT pin if it was pulled low if another
interrupt condition is queued on the Interrupt Stack it can
only pull the INT pin low when CS is high When CS is high
the CO pin is in the high-impedance state enabling the CO
pins of many devices to be multiplexed together
TL H 9151 – 12
TL H 9151 – 13
TL H 9151 – 14