TP3410J National Semiconductor, TP3410J Datasheet - Page 18

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
mode and the 2B
port(s) are in the high impedance state
BP1 Not Used
This bit is not used and should always be set to zero
BP2 Activation Breakpoint
This bit is effective only in LT mode It provides for the start-
up sequence to be either automatically controlled by the
TP3410 or for the external controller to be able to halt the
sequence at J7 The controller can complete start-up by
sending ‘‘AC’’ to the ACT register (X 440C) For more infor-
mation see Section 11 0 Activation Deactivation
BP2
9 5 Configuration Register CR3 Loopbacks
Line Loopbacks Select LB1 LB2 LBD
LB1 LB2 LBD bits when set
B1 B2 or D channel respectively from the line receive input
to the line transmit output They may be set separately or
together Each loopback is operated near the Bx and Br
digital interface pins (or Dx and Dr if the D port is selected)
These loopbacks may be either transparent that is data
received from the line is also passed on to the digital inter-
face or non-transparent in which case the selected chan-
nel bits on the digital interface are in the high impedance
state transparency is controlled by the TLB bit
Digital Loopbacks Select DB1 DB2 DBD
DB1 DB2 and DBD bits when set
B1 B2 or D channel respectively from the Bx input to the Br
output (or Dx and Dr if the D port is selected) They may be
set separately or together Each loopback is operated near
the digital interface pins if Format 3 is selected there is no
restriction on the time-slots selected for each direction
These loopbacks may be either transparent that is data
received from the Bx or Dx input is also transmitted to the
line or non-transparent in which case the selected channel
bits to the scrambler are forced low in LT mode or high in
NT mode transparency is controlled by the TLB bit
TLB Transparent Loop-Back Enabling
nel)
TLB
9 6 Configuration Register CR4 Device Control
A new configuration register (CR4) has been added to the
Rev 3 TP3410 device to allow control of new features
Please also see TP3410 Users Manual AN-913
Address X 2C
BP1
BP2
CR3 is set to X 00 at Power-On Reset
TLB
SH9
CR4 is set to X 0F at Power-On Reset
LB1
7
7
e
e
e
e
e
1 for Breakpoint enabled
1 for transparent loopbacks
AACT
0 for non-transparent loopbacks (B1 B2 or D chan-
0
0 for Breakpoint disabled
LB2
6
6
LBD
WS
5
5
a
D slots at the receive digital interface
333 Hz
DB1
4
Byte 2
4
Byte 2
e
DB2
1 loopback each individual
saif
3
3
e
1 turn each individual
(Continued)
TFB0
DBD
2
2
RFS
1
TLB
1
LFS
0
0
0
18
SH9 Software H9 Control Bit
In NT mode while SH9
or H8 H11 will enter the H9 state in response to receiving
‘‘dea
after 60 ms (to prevent a ‘‘hang up condition’’) to H12 With
SH9
H11 will generate a DP interrupt when it receives the ‘‘dea
H9 The device will still deactivate in response to loss of
signal Deactivating in this manner will however cause the
NT mode device to perform a cold start only on subsequent
activation attempts The WS bit may be set
device to attempt a warm start
AACT Activation Control Bit
AACT
modes AACT
behaves normally Auto-activation can be used in applica-
tions such as Linecard to allow the device to respond to an
incoming 10 kHz wake-up tone (LSD) by powering itself up
(PUP) and starting the activation procedure (AR) within the
device
WS Warm Start
If this bit is set
Start activation after a deactivation This function should
only be necessary where Warm Start is preferred but
SH9
333 Hz Maintenance Test Tone
333 Hz
modes (Bellcore requirement)
333 Hz
up (after PUP) state but not activated
Example of use
Write PUP X 2C1F to enable 333 Hz test tone X 2C0F to
disable 333 Hz tone
saif Select Analog Interface
saif
that is compatible with Rev 2 x devices saif
use of the alternative line interface circuit with 0
line-side of the transformer This circuit can provide benefit
for linecard applications where line powering of remote
NT1s and repeaters is required
Example of use
Write X 2C0F for standard line interface and X 2C07 for al-
ternative line interface
TFB0
TFB0
purposes TFB0
LFS and RFS Note that this function was controlled by the
TFB bit in TXM56 register in Rev 2 x devices The TFB bit in
TXM56 bit is now (Rev 3 x) active for one superframe only
if set to 0 by software a superframe will transmit febe
and then the TFB will be reset to 1 by the device The soft-
ware does not need to set it to 1
e
SH9
AACT
WS
333 Hz
saif
TFB0
0’’ bit but is prevented from transitioning to device state
e
e
e
e
e
e
e
e
1 indicates operation with the standard line interface
e
e
e
e
1 a TP3410 Rev 3 3 device in state H6 H7 or H8
0 (default state)
1 is required
1 (default state)
0 (default state)
e
e
0’’ for 3 consecutive superframes and then exit
0 forces transmit febe to 0 continuously for test
1 (default state)
0 disables it This test tone is to be used in power
0 (default state)
1 enables auto-activation in either LT or NT
0 (default state)
1 enables 333 Hz tone for Maintenance test
e
e
e
0 disables it (default state) and the device
1 a Rev 3 3 device will attempt Warm
1 allows normal operation controlled by
e
0 a rev 3 x device in state H6 H7
e
e
0 indicates
1 for the
on the
e
0