TP3410J National Semiconductor, TP3410J Datasheet - Page 17

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
9 0 COMMAND REGISTER FUNCTIONS
All addressing and bit-level functions are the same for both
the Microwire and GCI Monitor Channels except where not-
ed Register addresses are listed in Table II An asterisk
indicates the Power-on Reset state of each function The
device modes and Transmit M bits should be programmed
while the device is powered down
9 1 Writing to Command Registers
A command may be written to a register to modify its con-
tents by setting byte 1 bit 0
and the Time-Slot Assignment registers may also be read-
back to verify the contents by addressing each register with
byte 1 bit 0
waiting to be read during a command cycle it will return
X 0000 (No Change)
9 2 Reading Back Command Registers for Verification
To read back the current state of one of the write-able regis-
ters the appropriate readback command must first be load-
ed in via the control channel this will cause an interrupt to
be sent to the interrupt stack In Microwire mode the inter-
rupt must be serviced by a read cycle in which the com-
mand should be a NOP (or a new command) In this cycle
the previously addressed register is read back with byte 1
bit 0
tonomous one-way message in the Monitor Channel If any
other interrupt conditions should occur during the readback
command cycle the readback result will be queued at the
bottom of the stack and will not generate its interrupt or
message until all other interrupts are cleared
9 3 Configuration Register CR1 Digital Interface
FF1 FF0 Digital System Interface Frame Format
Selection
These bits are effective in Microwire Mode only (MW
They select the Digital Interface format as described in Sec-
tion 6
CK0 –CK2 Digital Interface Clock Select
In Microwire Mode only and if DSI Master is selected (CMS
for the BCLK output (In GCI Mode these bits have no ef-
fect ) The frequency of 256 kHz is not valid with Format 4
e
CR1 is set to X 00 at Power-On Reset
FF1
7
1) CK0–CK2 bits select from a choice of 5 frequencies
CK2
e
0
0
0
0
1
1 In GCI mode the interrupt stack generates an au-
Format
FF0
6
2
3
4
e
1
1 In Microwire Mode if the device has no data
CK1
CK2
0
0
1
1
0
5
CK1
4
CK0
Byte 2
0
1
0
1
0
e
FF1
CK0
0 Registers CR1 2 3 OPR
0
0
1
1
3
DDM
BCLK Frequency
1536 kHz Master
2048 kHz Master
2560 kHz Master
(Continued)
2
256 kHz Master
512 kHz Master
CMS
1
FF0
0
1
0
1
BEX
e
0
1)
17
DDM Delayed Data Mode Select
For Microwire mode see Section 6 1 FS Relationship to
Data In GCI Mode or Format 4 this bit has no effect
DDM
CMS DSI Clock Master Slave Select
In Microwire Mode (MW
CMS
Modes
CMS
Modes but when in LT Mode must also send X 1840 See
the TP3410 User’s Manual AN-913 Section 4 5 for details
In GCI Mode (MW
selects GCI Master or Slave
BEX B Channel Exchange
This command enables the two B channels to be ex-
changed as the data passes through the device between
the Digital Interface and the Line in both directions It should
not be used if any loopback is selected in the device
to B2
BEX
9 4 Configuration Register CR2 Device Modes
SSS Superframe Synchronization Select
This bit is effective in LT mode only in NT mode the SFS pin
is an output When SSS
chronizes the transmit superframe counter on the line
When SSS
NTS NT or LT Select
NTS
DEN D Channel Port Select
bits are transferred on the Br and Bx pins clocked by BCLK
The Dx pin must also be tied to GND for correct operation
When DEN
transferred on the Dr and Dx pins in a mode selected by the
DMO bit see Section 6 3
DMO D Channel Transfer Mode Select
This bit is significant only when the D channel port is select-
ed (DEN bit
When DMO
and Dr pins in a continuous mode at 16 kbit s on the falling
and rising edges of DCLK respectively see Figure 4
When DMO
and Dr pins in a burst mode at the BCLK frequency when
the assigned time-slots are active see Figure 5
DD 2B
as the line is completely synchronized
When DD
data transmitted to line is preset to send scrambled 1’s with
the device in NT mode or scrambled 0’s if the device is in LT
DDM
BEX
CR2 is set to X 00 at Power-On Reset
NTS
When DEN
When DD
SSS
7
e
e
e
e
e
e
e
e
a
1 for B channels exchanged B1 to B2 and B2 to B1
1 for NT Mode
1 for delayed data mode (see Figure 12 )
1 for DSI Master may be used in either LT or NT
0 for DSI Slave may be used in either LT or NT
0 for B channels mapped direct B1 to B1 and B2
0 for LT Mode
NTS
D Data Disabling
0 for non-delayed data mode (see Figure 11 )
e
6
e
e
e
e
e
e
e
1 B and D channel transfer is inhibited The
1 SFS is an output superframe marker pulse
0 2B
1 the D channel port is enabled D bits are
1 D channel data is shifted in and out on Dx
0 D channel data is shifted in and out on Dx
1)
0 the D channel port is disabled and the D
DMO
e
5
a
D channel transfer is enabled as soon
0) this bit has no effect the MO pin
e
e
Byte 2
DEN
1)
4
0 SFS is an input which syn-
DD
3
BP1
2
BP2
1
0
0