PEB 24911 H V1.3 Lantiq, PEB 24911 H V1.3 Datasheet - Page 8

• Manufacturer Part Number: PEB 24911 H V1.3
• Manufacturer: Lantiq

Specifications of PEB 24911 H V1.3

• Lead Free Status / Rohs Status: Supplier Unconfirmed

List of Figures
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Data Sheet
Sets 8
DFE-Q/ AFE 2nd Generation Chip Set . . . . . . . . . . . . . . . . . . . . . . . . . 1
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
16-Line Card Application with DELIC Solution. . . . . . . . . . . . . . . . . . . . 5
16-Line Card Application with ELIC®/ IDEC® Solution . . . . . . . . . . . . . 6
Connecting Two AFE/DFE-Q Chip Sets . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Clocking Scheme for More Than Two DFE-Q/AFE Chip
Pin Configuration (63 of 64 used) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram and Data Flow (DFE-Q V2.1 + AFE V2.1) . . . . . . . . . . 20
Clock Supply and Data Exchange between Master and Slave . . . . . . 21
Multiplexed Frame Structure of the IOM®-2 Interface . . . . . . . . . . . . . 23
Superframe Marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Handshake Protocol with a 2-Byte Monitor Message/Response . . . . . 26
Abortion of Monitor Channel Transmission . . . . . . . . . . . . . . . . . . . . . 28
Interface to the Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Frame Structure on SDX/SDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
U-Superframe Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
U-Basic Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MON-0/2 - M-Bit Correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maintenance Channel Filtering Options. . . . . . . . . . . . . . . . . . . . . . . . 40
M4 Bit Report Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
M4, M5, M6 Bit Control in Transmit Direction . . . . . . . . . . . . . . . . . . . 44
M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 44
EOC-Procedure in Auto- and Transparent Mode. . . . . . . . . . . . . . . . . 49
CRC-Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Scrambler/ Descrambler Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Explanation of the State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
State Transition Diagram in LT-Mode . . . . . . . . . . . . . . . . . . . . . . . . . 57
Complete Activation Initiated by LT . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Activation with ACT-Bit Status Ignored by the Exchange . . . . . . . . . . 75
Complete Activation Initiated by TE . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Complete Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
U Only Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
LT Initiated Activation with U-Interface Active . . . . . . . . . . . . . . . . . . . 82
TE-Activation with U Active and Exchange Control (case 1) . . . . . . . . 84
TE-Activation with U Active and no Exchange Control (case 2) . . . . . 86
Deactivation of S/T Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Test Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Complete Loopback Options in the NT . . . . . . . . . . . . . . . . . . . . . . . . 91
Loopbacks Featured by Register LOOP . . . . . . . . . . . . . . . . . . . . . . . 96
Block Error Counter Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Total Power Measurement Set-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PEF 24911
2001-07-16
Page