PEB 24911 H V1.3 Lantiq, PEB 24911 H V1.3 Datasheet - Page 132

• Manufacturer Part Number: PEB 24911 H V1.3
• Manufacturer: Lantiq

Specifications of PEB 24911 H V1.3

• Lead Free Status / Rohs Status: Supplier Unconfirmed

FEBE
6.4.3
The M-Bit Filter register defines the validation algorithm received Maintenance channel
bits (M1-M6) of the U-interface have to undergo before they are approved and passed
on to the system interface. The MFILT register is unique for all ports. Writing into MFILT
from one channel affects the setting of all channels.
M-bit changes are reported to the system environment by MON-0 (EOC) or MON-2 (M4-
M6) messages via IOM
three different filter functions are supported, Triple-Last-Look (TLL), CRC check and On
Change.
• Triple-Last-Look (TLL)
• CRC
• On Change
Some M4 bits, ACT, DEA and UOA, have two destinations, the state machine and the
system interface. Regarding these bits Triple-Last-Look (TLL) is applied by default
before the changed status is input to the state machine. Via bit no. 5 of the MFILT
register the user can decide whether the M4 bits which are input to the state machine
shall be approved by TLL (Bellcore requirement) or by the same verification mode as
selected for the issue of a MON-2 message.
The MFILT register setting is evaluated each time the DFE-Q V2.1 leaves the
“Deactivated” state. For further information on the handling regarding the Maintenance
channel please refer to
Data Sheet
A change of M-bit data has to be received in three consecutive U-frames until it is
approved valid and reported to the system interface.
A change of M-bit data is only reported to the system interface if no CRC violation has
been detected.
The forwarding of M-bit changes is delayed by 12 ms (= 1x U-superframe) if received
M-bits are CRC covered. This way the M-bit data is checked with the actual CRC sum
which is received one U-superframe later.
Every time the M-bit status has changed a MON-0 or MON-2 message is issued.
MFILT - M-Bit Filter Options
Enable/Disable external write access to FEBE Bit in register M56W
0 =
1 =
external access to FEBE bit disabled - FEBE bit is set by internal
FEBE counter logic
external access to FEBE bit enabled - FEBE bit is controlled by
MON-2
Chapter
®
-2. To lower processor load due to faulty monitor messages
3.8.
122
Register Description
PEF 24911
2001-07-16