PEB 24911 H V1.3 Lantiq, PEB 24911 H V1.3 Datasheet - Page 16

• Manufacturer Part Number: PEB 24911 H V1.3
• Manufacturer: Lantiq

Specifications of PEB 24911 H V1.3

• Lead Free Status / Rohs Status: Supplier Unconfirmed

•
Figure 4
Figure 5
DFE-Q chip sets:
One AFE-PLL generates the synchronized 15.36 MHz clock and provides the master
clock at pin CL15 for the other 3 devices. The internal PLL of the first AFE synchronizes
the 15.36 MHz master clock onto a PTT reference clock of either 8 kHz or 2048 kHz.
Infineon recommends to feed the FSC clock input of the DFE-Q V2.1 and the PLL
reference clock input (pin CLOCK) of the AFE from the same clock source.
The PLL of the second AFE is deactivated. The 15.36 MHz master clock is applied at pin
CL15. CL15 is configured as input if XIN is clamped either to VDD or to VSS. Pin XOUT
has to be left open and CLOCK shall be tied to GND.
Data Sheet
1
2
3
4
shows how an 8 channel line card application is realized by use of two AFE/
Te st Unit
16-Line Card Application with ELIC
Q-IHPC
PEB 2426
PEF 24902
AFE
V2.1
6
PEF 24911
DFE-Q
V2.1
®
/ IDEC
®
PEB 2075
IOM
IDEC
Solution
®
-2
µC-Bus
PEB 20550
ELIC
C165/6
µC
Introduction
PEF 24911
2001-07-16
Highw a y
Signalling
PCM
appl_elic.v sd