ispPAC-POWR6AT6-01SN32I Lattice, ispPAC-POWR6AT6-01SN32I Datasheet - Page 29

• Manufacturer Part Number: ispPAC-POWR6AT6-01SN32I
• Description: Supervisory Circuits Prec Prog Pwr Supply Seq Mon Trim IND
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR6AT6-01SN32I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: Adjustable
• Overvoltage Threshold: Adjustable
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFNS-32
• Minimum Operating Temperature: - 40 C
• Applications: Power Supply Controller/Monitor
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 3-7. ispPAC-POWR6AT6 TAP Instruction Table
BYPASS is one of the three required JTAG instructions. It selects the Bypass Register to be connected between
TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the
ispPACPOWR6AT6.
The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/
PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPAC-
POWR6AT6 has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this
instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 3-7.
The EXTEST (external test) instruction is required and would normally place the device into an external boundary
test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the
ispPAC-POWR6AT6 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000).
The optional IDCODE (identification code) instruction is incorporated in the ispPAC-POWR6AT6 and leaves it in its
functional mode when executed. It selects the Device Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer,
device type and version code (Figure 3-27). Access to the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for
this instruction is defined by Lattice as shown in Table 3-7.
EXTEST
BULK_ERASE
PROGRAM_SECURITY
DISCHARGE
PROGRAM_ENABLE
IDCODE
UES_READ
UES_PROGRAM
SAMPLE
PROGRAM_DISABLE
RESET
ERASE_DONE_BIT
CFG_VERIFY
CFG_ERASE
CFG_ADDRESS
CFG_DATA_SHIFT
CFG_PROGRAM
PROGRAM_DONE_BIT
BYPASS
Instruction
Command Code
0000 0000
0000 0011
0000 1001
0001 0100
0001 0101
0001 0110
0001 0111
0001 1010
0001 1100
0001 1110
0010 0010
0010 0100
0010 1000
0010 1001
0010 1011
0010 1101
0010 1110
0010 1111
1111 1111
External Test - Defaults to BYPASS
Bulk erase device
Program security fuse
Fast VPP discharge
Enable program mode
Read contents of manufacturer ID code (32 bits)
Read contents of UES register from E
Program UES bits into E
Sample/Preload - Defaults to BYPASS
Disable program mode
Resets device (refer to reset command via JTAG or I
sheet)
Erases the DONE bit only
Verify the configuration data
Erase just the configuration data
Select the configuration address register (4 bits)
Configuration data shift (56 bits)
Program configuration data
Programs the DONE bit
Bypass - Connect TDO to TDI
3-29
2
CMOS
Comments
ispPAC-POWR6AT6 Data Sheet
2
CMOS (32 bits)
2
C section of this data