ispPAC-POWR6AT6-01SN32I Lattice, ispPAC-POWR6AT6-01SN32I Datasheet - Page 16

• Manufacturer Part Number: ispPAC-POWR6AT6-01SN32I
• Description: Supervisory Circuits Prec Prog Pwr Supply Seq Mon Trim IND
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR6AT6-01SN32I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: Adjustable
• Overvoltage Threshold: Adjustable
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFNS-32
• Minimum Operating Temperature: - 40 C
• Applications: Power Supply Controller/Monitor
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR6AT6 Data Sheet
It should also be noted that whenever the VPS0 and VPS1 pins are not both low, they effectively stop closed-loop
trim the same way the CLTENb pin does when it goes high. That is, whenever an alternate trim mode (other than
VPS0=0 and VPS1=0) is selected, the trim process is suspended as described above. Assuming the CLTENb pin
is asserted, when both VPS0 and VPS1 are low again, closed-loop trimming will resume where it left off.
It is recommended that the CLTENb pin not be activated until after any necessary power supply sequencing is
completed to prevent an “open loop” condition from occurring. Otherwise, if control of when closed-loop trimming
begins is not critical, the CLTENb pin can be tied to ground. This will cause closed-loop trim to begin immediately
after the initial power on of the ispPAC-POWR6AT6 is completed.
Closed Loop Trim Start-up Behavior
The contents of the closed loop register, upon power-up, will contain a value 80h (Bipolar-zero) value. The DAC
output voltage will be equal to the programmed Offset voltage. Usually under this condition, the power supply out-
put will be close to its nominal voltage. If the power supply trimming should start after reaching its desired output
2
voltage, the corresponding DAC code can be loaded into the closed loop trim register through I
C (same address
2
as the DAC register I
C mode) before activating the CLTENb pin.
Details of the Digital to Analog Converter (DAC)
Each TrimCell has an 8-bit bipolar DAC to set the trimming voltage (Figure 3-11). The full-scale output voltage of
the DAC is +/- 320 mV. A code of 80H results in the DAC output set at its bi-polar zero value.
The voltage output from the DAC is added to a programmable offset value and the resultant voltage is then applied
to the trim output pin. The offset voltage is typically selected to be approximately equal to the DC-DC converter
open circuit trim node voltage. This results in maximizing the DC-DC converter output voltage range.
2
The programmed offset value can be set to 0.6V, 0.8V, 1.0V or 1.25V. This value selection is stored in E
CMOS
memory and cannot be changed dynamically.
Figure 3-11. Vbpz Offset Voltage is Added to DAC Output Voltage to Derive Trim Pad Voltage
TrimCell X
DAC
8
TRIMx
From
7 bits + Sign
Pad
Trim Registers
(-320mV to +320mV)
Vbpz Offset
(0.6V,0.8V,1.0V,1.25V)
2
E
CMOS
2
RESET Command via JTAG or I
C
2
Issuing a reset instruction via JTAG or I
C will force all trim outputs selected for digital closed-loop trim control back
to their initial output level (code 80h + Vbpz). After that, assuming the CLTENb is still asserted, digital closed loop
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